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Part Number 9DBU0541
Description 5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
Manufacture IDT
Total Page 17 Pages
PDF Download Download 9DBU0541 Datasheet PDF

Features: 5-Output 1.5V PCIe Gen1-2-3 Fanout Buffe r with Zo=100ohms 9DBU0541 DATASHEET Description The 9DBU0541 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated terminations for direct connection to 100 transmi ssion lines. The device has 5 output en ables for clock management, and 3 selec table SMBus addresses. Recommended Appl ication 1.5V PCIe Gen1-2-3 Fanout Buffe r (FOB) Output Features • 5 1–167MH z Low-Power (LP) HCSL DIF pairs with ZO =100 Key Specifications • DIF addi tive cycle-to-cycle jitter < 5ps • DI F output-to-output skew < 60ps • DIF additive phase jitter is < 300fs rms fo r PCIe Gen3 • DIF additive phase jitt er < 350fs rms for SGMII Features/Bene fits • Integrated terminations; save 20 resistors compared to standard HCSL outputs • 35mW typical power consumpt ion; eliminates thermal concerns • Sp read Spectrum (SS) compatible; allows S S for EMI reduction • OE# pins; suppo rt DIF power management • HCSL-compatible differential input;.

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9DBU0541 datasheet
5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer
with Zo=100ohms
9DBU0541
DATASHEET
Description
The 9DBU0541 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. It has integrated terminations for direct
connection to 100transmission lines. The device has 5
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Fanout Buffer (FOB)
Output Features
5 1–167MHz Low-Power (LP) HCSL DIF pairs with
ZO=100
Key Specifications
DIF additive cycle-to-cycle jitter < 5ps
DIF output-to-output skew < 60ps
DIF additive phase jitter is < 300fs rms for PCIe Gen3
DIF additive phase jitter < 350fs rms for SGMII
Features/Benefits
Integrated terminations; save 20 resistors compared to
standard HCSL outputs
35mW typical power consumption; eliminates thermal
concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
5 × 5 mm 32-VFQFPN; minimal board space
Block Diagram
vOE(4:0)#
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
5
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBU0541 MARCH 9, 2017
1 ©2017 Integrated Device Technology, Inc.

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