Serial Memory. RM25C64C Datasheet

RM25C64C Memory. Datasheet pdf. Equivalent

Part RM25C64C
Description 64Kbit 2.7V Minimum Non-volatile Serial Memory
Feature RM25C64C 64Kbit 2.7V Minimum Non-volatile Serial Memory SPI Bus Features  Memory array: 64Kbit EEPR.
Manufacture Adesto
Datasheet
Download RM25C64C Datasheet



RM25C64C
RM25C64C
64Kbit 2.7V Minimum
Non-volatile Serial Memory
SPI Bus
Features
Memory array: 64Kbit EEPROM-compatible serial memory
Single supply voltage: 2.7V - 3.6V
Serial peripheral interface (SPI) compatible
Supports SPI modes 0 and 3
1.6MHz maximum clock rate for normal read
5MHz maximum clock rate for fast read
Page size: 32 byte
-Byte and Page Write from 1 to 32 bytes
-Byte Write within 25µs
-Page Write within 1ms
Self-timed erase and write cycles
Page or chip erase capability
1mA read current, 1.5mA write current, 5µA power-down current
8-lead packages
RoHS-compliant and halogen-free packaging
Based on Adesto's proprietary CBRAM® technology
Data Retention: 10 years
Endurance: 25,000 Write Cycles
Unlimited Read Cycles
Description
The Mavriq™ RM25C64C is an EEPROM-compatible, 64Kbit non-volatile serial
memory utilizing Adesto's CBRAM resistive memory technology. The memory device
uses a single low-voltage supply ranging from 2.7V to 3.6V.
The RM25C64C is accessed through a 4-wire SPI interface consisting of a Serial Data
Input (SDI), Serial Data Output (SDO), Serial Clock (SCK), and Chip Select (CS). The
maximum clock (SCK) frequency in normal read mode is 1.6MHz. In fast read mode
the maximum clock frequency is 5MHz.
Writing into the device can be done from one to 32 bytes at a time. All writing is
internally self-timed. The device also features an Erase which can be performed on
32-byte pages, or the whole chip. Writing a single byte to the Mavriq RM25C32C
device consumes only 10% of the energy required by a Byte Write operation of
EEPROM devices of similar size.
DS-RM25C64C–064F–1/2018



RM25C64C
1. Block Diagram
VCC
Status
Registers
&
Control
Logic
SCK
SDI
SDO
CS
WP
HOLD
GND
SPI
Interface
Address
Latch
&
Counter
I/O Buffers and Data
Latches
Page Buffer
Y-Decoder
64Kb
CBRAM
Memory
Figure 1-1. Block Diagram
RM25C64C
DS-RM25C64C–064F–1/2018
2





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