Fanout Buffer. 83904-02 Datasheet

83904-02 Buffer. Datasheet pdf. Equivalent

Part 83904-02
Description Crystal-to-LVCMOS / LVTTL Fanout Buffer
Feature Low Skew, 1-to-4, Crystal-to-LVCMOS/ LVTTL Fanout Buffer 83904-02 Data Sheet GENERAL DESCRIPTION T.
Manufacture IDT
Datasheet
Download 83904-02 Datasheet



83904-02
Low Skew, 1-to-4, Crystal-to-LVCMOS/
LVTTL Fanout Buffer
83904-02
Data Sheet
GENERAL DESCRIPTION
The 83904-02 is a low skew, high performance 1-to-4 Crystal-to-
LVCMOS Fanout Buffer.The 83904-02 has selectable single-ended
clock or two crystal-oscillator inputs. There is an output enable to
disable the outputs by placing them into a high-impedance state.
Guaranteed output and part-to-part skew characteristics
make the 83904-02 ideal for those applications demand-
ing well defined performance and repeatability.
BLOCK DIAGRAM
Pullup
OE
Pulldown
CLK_SEL0
CLK_SEL1 Pulldown
FEATURES
Four LVCMOS/LVTTL outputs,
19Ω typical output impedance @ V = V = 3.3V
DD DDO
Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
Crystal input frequencry range: 12MHz – 38.88MHz
Output frequency: 200MHz (maximum)
Output Skew: 40ps (maximum) @ V = V = 3.3V
DD DDO
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz – 1MHz): 0.16ps (typical) @ V = V = 3.3V
DD DDO
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ..............-118.4 dBc/Hz
1kHz ..............-141.5 dBc/Hz
10kHz ..............-157.2 dBc/Hz
100kHz ..............-157.2 dBc/Hz
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
XTAL_IN0
XTAL_OUT0
OSC
00
XTAL_IN1
XTAL_OUT1
OSC
CLK Pulldown
01
10
11
PIN ASSIGNMENT
Q0
CLK_SEL0 1
16 VDDO
XTAL_OUT0 2 15 Q0
XTAL_IN0 3 14 Q1
VDD 4
13 GND
Q1 XTAL_IN1 5 12 Q2
XTAL_OUT1 6 11 Q3
CLK_SEL1 7
10 VDDO
CLK 8
9 OE
Q2
83904-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
Q3 package body
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 17, 2016



83904-02
83904-02 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 7
CLK_SEL0,
CLK_SEL1
Input
Pulldown
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS / LVTTL interface levels.
2, 3
XTAL_OUT0,
XTAL_IN0
Input
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
4 V Power
DD
5, 6
XTAL_IN1,
XTAL_OUT1
Input
Positive supply pin.
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
8 CLK Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
9
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
10, 16
V
DDO
Power
11, 12, 14, 15 Q3, Q2, Q1, Q0 Output
Output supply pins.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
13
GND
Power
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
PD
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
R Output Impedance
OUT
Test Conditions
V = 3.465V
DDO
V = 2.625V
DDO
V = 2.0V
DDO
V = 3.3V
DDO
V = 2.5V
DDO
V = 1.8V
DDO
Minimum
Typical
4
51
51
8
7
7
19
21
32
Maximum
Units
pF
kΩ
kΩ
pF
pF
pF
Ω
Ω
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
CLK_SEL1 CLK_SEL0
00
01
10
11
Reference
XTAL0 (default)
XTAL1
CLK
CLK
©2016 Integrated Device Technology, Inc
2
Revision A March 17, 2016





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