CLOCK GENERATOR. Si52147 Datasheet

Si52147 GENERATOR. Datasheet pdf. Equivalent

Part Si52147
Description CLOCK GENERATOR
Feature Si52147 PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR Features  PCI-Express Gen .
Manufacture Silicon Laboratories
Datasheet
Download Si52147 Datasheet



Si52147
Si52147
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT
CLOCK GENERATOR
Features
PCI-Express Gen 1, Gen 2, Gen 3, Up to nine PCI-Express clock outputs
and Gen 4 common clock compliant I2C support with readback
Gen 3 SRNS Compliant
capabilities
Supports Serial-ATA (SATA) at
Triangular spread spectrum profile
100 MHz
for maximum electromagnetic
Low power push-pull HCSL
interference (EMI) reduction
compatible differential outputs
No termination resistors required
Output enable pins for all clocks
Spread enable pin
25 MHz crystal input or clock input
Industrial temperature:
–40 to 85 oC
3.3 V power supply
48-pin QFN package
Applications
Network attached storage
Multi-function printer
Description
Wireless access point
Servers
The Si52147 is a high-performance, PCIe clock generator that can source nine
PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are compliant
to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common clock
specifications. The device has six hardware output enable control pins for
enabling and disabling differential outputs. A spread spectrum control pin for EMI
reduction is also available. The small footprint and low power consumption makes
the Si52147 the ideal clock solution for consumer and embedded applications.
Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock
Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
Ordering Information:
See page 20.
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37
VDD_DIFF 1
36 DIFF8
VDD_DIFF 2
35 DIFF8
OE_DIFF01 3
34 VDD_DIFF
OE_DIFF11 4
SSON2 5
VSS_DIFF 6
VSS_DIFF 7
OE_DIFF21 8
OE_DIFF31 9
OE_DIFF[4:5]1 10
OE_DIFF[6:8]1 11
VDD_DIFF 12
49
GND
33 DIFF7
32 DIFF7
31 DIFF6
30 DIFF6
29 VSS_DIFF
28 DIFF5
27 DIFF5
26 DIFF4
25 DIFF4
13 14 15 16 17 18 19 20 21 22 23 24
XIN/CLKIN
XOUT
PLL1
(SSC)
Divider
SCLK
SDATA
CKPWRGD/PDB
OE [8:0]
SSON
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
DIFF6
DIFF7
DIFF8
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
Rev. 1.4 4/16
Copyright © 2016 by Silicon Laboratories
Si52147



Si52147
Si52147
2 Rev. 1.4





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