8Gb C-die. M378A5244CB0 Datasheet

M378A5244CB0 C-die. Datasheet pdf. Equivalent

Part M378A5244CB0
Description 288pin Unbuffered DIMM based on 8Gb C-die
Feature Rev. 1.4, Apr. 2018 M378A5244CB0 M378A1K43CB2 M378A2K43CB1 288pin Unbuffered DIMM based on 8Gb C-die.
Manufacture Samsung
Datasheet
Download M378A5244CB0 Datasheet



M378A5244CB0
Rev. 1.4, Apr. 2018
M378A5244CB0
M378A1K43CB2
M378A2K43CB1
288pin Unbuffered DIMM
based on 8Gb C-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
© 2018 Samsung Electronics Co., Ltd.GG All rights reserved.
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M378A5244CB0
Unbuffered DIMM
datasheet
Rev. 1.4
DDR4 SDRAM
Revision History
Revision No.
History
1.0 - First SPEC. Release
1.1 - Deletion of Function Block Diagram [M378A1K43CB2] on page 11
- Change of Physical Dimensions [M378A1K43CB1] on page 41
1.11 - Correction of Typo
1.2 - Change of Physical Dimensions [M378A1K43CB1] on page 41
1.3 - Addition of DDR4-2666
1.4 - Correct typo in Key features.
- Update Input/output functional description.
- Update Single-ended AC & DC Input Levels for Command and Address
table.
- Update Differential AC and DC Input Levels table.
- Update Single-ended Levels for CK_t, CK_c table.
- Add Address, Command and Control Overshoot and Undershoot specifica-
tions.
- Add Data, Strobe and Mask Overshoot and Undershoot Specifications.
- Update Cross Point Voltage for Differential Input Signals (CK)
- Add CMOS rail to rail Input Levels.
- Add AC and DC Logic Input Levels for DQS Signals.
- Add Peak voltage calculation method.
- Add Differential Input Cross Point Voltage (DQS).
- Add Differential Input Slew Rate Definition DQS).
- Add AC AND DC OUTPUT MEASUREMENT LEVELS.
- Correct Single-ended AC & DC Output Levels table.
- Update Speed Bin Table Note.
- Update Timing parameters by speed grade.
- Add Rounding Algorithms.
- Add The DQ input receiver compliance mask for voltage and timing.
- Add Command, Control, and Address Setup, Hold, and Derating.
- Add DDR4 Function Matrix
Draft Date
27th Jun. 2016
29th Jun. 2016
7th Mar. 2017
23h Mar. 2017
31th Mar. 2017
27th Apr, 2018
Remark
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Final
Editor
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
J.Y.Lee
C.M.Kang
J.Y.Bae
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