9QXL2000B Datasheet | 20-output very-low-additive phase jitter fanout buffer





(Datasheet) 9QXL2000B Datasheet PDF Download

Part Number 9QXL2000B
Description 20-output very-low-additive phase jitter fanout buffer
Manufacture IDT
Total Page 23 Pages
PDF Download Download 9QXL2000B Datasheet PDF

Features: 20-Output DB2000Q 9QXL2000B Datasheet Description The 9QXL2000B is a 20-outpu t very-low-additive phase jitter fanout buffer for PCIe Gen4 and Gen5. It offe rs integrated terminations for 85Ω tr ansmission lines with individual output impedance trim and via SMBus registers . PCIe Clocking Architectures Supported ▪ Common Clocked (CC) ▪ Independen t Reference (IR) with and without sprea d spectrum Typical Applications ▪ Ser vers ▪ Storage ▪ Networking ▪ SSD s Features ▪ Low-Power HCSL (LP-HCSL ) 85Ω outputs eliminate 80 resistors, saving 130mm2 of area ▪ Low-Power HC SL (LP-HCSL) outputs reduce device powe r consumption by 50% ▪ 8 OE# pins con figurable to control up to 20 outputs 9 selectable SMBus addresses ▪ Spr ead spectrum compatible ▪ 10 × 10 mm 72-VFQFPN package Output Features ▪ 20 Low-Power HCSL (LP-HCSL) 85Ω outpu t pairs Key Specifications ▪ Output-t o-output skew: < 50ps ▪ Additive phas e jitter: DB2000Q filter < 40fs rms ▪ Additive Phase jitter: .

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20-Output DB2000Q
9QXL2000B
Datasheet
Description
The 9QXL2000B is a 20-output very-low-additive phase jitter
fanout buffer for PCIe Gen4 and Gen5. It offers integrated
terminations for 85transmission lines with individual output
impedance trim and via SMBus registers.
PCIe Clocking Architectures
Supported
Common Clocked (CC)
Independent Reference (IR) with and without spread spectrum
Typical Applications
Servers
Storage
Networking
SSDs
Features
Low-Power HCSL (LP-HCSL) 85outputs eliminate 80
resistors, saving 130mm2 of area
Low-Power HCSL (LP-HCSL) outputs reduce device power
consumption by 50%
8 OE# pins configurable to control up to 20 outputs
9 selectable SMBus addresses
Spread spectrum compatible
10 × 10 mm 72-VFQFPN package
Output Features
20 Low-Power HCSL (LP-HCSL) 85output pairs
Key Specifications
Output-to-output skew: < 50ps
Additive phase jitter: DB2000Q filter < 40fs rms
Additive Phase jitter: PCIe Gen4 filter < 40fs rms
Additive Phase jitter: PCIe Gen5 filter < 20fs rms
DB2000Q v1.1 pinout
Block Diagram
VDDR
VDD x 6
DIF_IN#
DIF_IN
DIF_19#
DIF_19
^vSADR 0_tri
^vSADR1_tri
SMBCLK
SMBDAT
^CKPWRGD _PD#
OE[5:12]#
SMBus
Engine
Factory
Configuration
Control Logic
20
outputs
DIF_0#
DIF_0
GNDR
EPAD/GND
GND x 5
©2019 Integrated Device Technology, Inc
1
February 15, 2019

                    
                    






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