RF DAC. ad9171 Datasheet

ad9171 DAC. Datasheet pdf. Equivalent


Analog Devices ad9171
Data Sheet
FEATURES
Supports single-band wireless applications
1 complex data input channel per RF DAC
516 MSPS maximum complex input data rate per input
channel
1 independent NCO per input channel
Proprietary, low spurious and distortion design
2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output
Flexible 8-lane, 15.4 Gbps JESD204B interface
Supports single-band use cases
Supports 12-bit high density mode for increased data
throughput
Multiple chip synchronization
Supports JESD204B Subclass 1
Selectable interpolation filter for a complete set of input
data rates
2×, 3×, 4×, and 6× configurable data channel interpolation
6× and 8× configurable final interpolation
Final 48-bit NCO that operates at the DAC rate to support
frequency synthesis up to 3.1 GHz
Transmit enable function allows extra power saving and
downstream circuitry protection
High performance, low noise PLL clock multiplier
Supports 6.2 GSPS DAC update rate
Observation ADC clock driver with selectable divide ratios
Low power
1.45 W at 6 GSPS, single-channel mode
10 mm × 10 mm, 144-ball BGA_ED with metal enhanced
thermal lid, 0.80 mm pitch
APPLICATIONS
Wireless communications infrastructure
Single-band base station radios
Instrumentation, automatic test equipment (ATE)
Dual, 16-Bit, 6.2 GSPS
RF DAC with Single Channelizer
AD9171
GENERAL DESCRIPTION
The AD9171 is a high performance, dual, 16-bit digital-to-analog
converter (DAC) that supports DAC sample rates to 6.2 GSPS.
The device features an 8-lane, 15.4 Gbps JESD204B data input port,
a high performance, on-chip DAC clock multiplier, and digital
signal processing capabilities targeted at single-band direct to
radio frequency (RF) wireless applications.
The AD9171 features one complex data input channels per RF
DAC. Each data input channel includes a configurable gain
stage, an interpolation filter, and a channel numerically
controlled oscillator (NCO) for flexible, frequency planning. The
device supports up to a 516 MSPS complex data rate per input
channel.
The AD9171 is available in a 144-ball BGA_ED package.
PRODUCT HIGHLIGHTS
1. Supports one complex data input channel per RF DAC at a
maximum complex input data rate of 513 MSPS with 12-bit
resolution and 516 MSPS with 16-bit resolution options.
There is one independent NCO per input channel.
2. Low power dual converter decreases the amount of power
consumption needed in high bandwidth and multichannel
applications.
Rev. 0
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ad9171 Datasheet
Recommendation ad9171 Datasheet
Part ad9171
Description Dual 16-Bit 6.2 GSPS RF DAC
Feature ad9171; Data Sheet FEATURES Supports single-band wireless applications 1 complex data input channel per RF D.
Manufacture Analog Devices
Datasheet
Download ad9171 Datasheet




Analog Devices ad9171
AD9171
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Power Supply DC Specifications ................................................ 5
Serial Port and CMOS Pin Specifications ................................. 6
Digital Input Data Timing Specifications ................................. 7
JESD204B Interface Electrical and Speed Specifications ........ 8
Input Data Rates and Signal Bandwidth Specifications .......... 8
AC Specifications.......................................................................... 9
Absolute Maximum Ratings.......................................................... 11
Reflow Profile.............................................................................. 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 18
Theory of Operation ...................................................................... 19
Serial Port Operation ..................................................................... 20
Data Format ................................................................................ 20
Serial Port Pin Descriptions...................................................... 20
Serial Port Options ..................................................................... 20
REVISION HISTORY
1/2018—Revision 0: Initial Version
Data Sheet
JESD204B Serial Data Interface.................................................... 22
JESD204B Overview .................................................................. 22
Physical Layer ............................................................................. 24
Data Link Layer .......................................................................... 26
Syncing LMFC Signals............................................................... 29
Transport Layer .......................................................................... 34
JESD204B Test Modes ............................................................... 35
JESD204B Error Monitoring..................................................... 37
Digital Datapath ............................................................................. 40
Total Datapath Interpolation .................................................... 40
Channel Digital Datapath ......................................................... 41
Main Digital Datapath ............................................................... 44
Interrupt Request Operation ........................................................ 50
Interrupt Service Routine.......................................................... 50
Applications Information .............................................................. 51
Hardware Considerations ......................................................... 51
Analog Interface Considerations.................................................. 54
DAC Input Clock Configurations ............................................ 54
Clock Output Driver.................................................................. 56
Analog Outputs .......................................................................... 56
Start-Up Sequence.......................................................................... 57
Register Summary .......................................................................... 64
Register Details ............................................................................... 72
Outline Dimensions ..................................................................... 133
Ordering Guide ........................................................................ 133
Rev. 0 | Page 2 of 133



Analog Devices ad9171
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SERDIN0±
SERDIN7±
SYNCOUT0±
SYNCOUT1±
CHANNEL 0 GAIN
N
SERDES
JESD204B
CHANNEL 1 GAIN
N
NCO
AD9171
PA PROTECT
M
RAMP UP/
DOWN GAIN
NCO
DAC 0
NCO
PA PROTECT
M
RAMP UP/
DOWN GAIN
NCO
DAC 1
SYNCHRONIZATION
LOGIC
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
DAC ALIGN
DETECT
CLOCK DIVIDER
÷1, ÷2, ÷3, ÷4
PLL
÷2, ÷3
RESET
VREF
SPI
CLOCK
RECEIVER
CLOCK
DRIVER
CLOCK
RECEIVER
AD9171
DAC0±
DAC1±
Figure 1. Functional Block Diagram
Rev. 0 | Page 3 of 133







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