RF DAC. AD9173 Datasheet

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AD9173 Datasheet
Recommendation AD9173 Datasheet
Part AD9173
Description Dual 16-Bit 12.6 GSPS RF DAC
Feature AD9173; Data Sheet FEATURES Supports multiband wireless applications 3 bypassable, complex data input channe.
Manufacture Analog Devices
Datasheet
Download AD9173 Datasheet




Analog Devices AD9173
Data Sheet
FEATURES
Supports multiband wireless applications
3 bypassable, complex data input channels per RF DAC
1.54 GSPS maximum complex input data rate per input
channel
1 independent NCO per input channel
Proprietary, low spurious and distortion design
2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output
Flexible 8-lane, 15.4 Gbps JESD204B interface
Supports single-band and multiband use cases
Supports 12-bit high density mode for increased data
throughput
Multiple chip synchronization
Supports JESD204B Subclass 1
Selectable interpolation filter for a complete set of input
data rates
1×, 2×, 3×, 4×, 6×, and 8× configurable data channel
interpolation
1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation
Final 48-bit NCO that operates at the DAC rate to support
frequency synthesis up to 6 GHz
Transmit enable function allows extra power saving and
downstream circuitry protection
High performance, low noise PLL clock multiplier
Supports 12.6 GSPS DAC update rate
Observation ADC clock driver with selectable divide ratios
Low power
2.55 W at 12 GSPS, dual channel mode
10 mm × 10 mm, 144-ball BGA_ED with metal enhanced
thermal lid, 0.80 mm pitch
APPLICATIONS
Wireless communications infrastructure
Multiband base station radios
Microwave/E-band backhaul systems
Instrumentation, automatic test equipment (ATE)
Dual, 16-Bit, 12.6 GSPS
RF DAC with Channelizers
AD9173
GENERAL DESCRIPTION
The AD9173 is a high performance, dual, 16-bit digital-to-analog
converter (DAC) that supports DAC sample rates to 12.6 GSPS.
The device features an 8-lane, 15.4 Gbps JESD204B data input port,
a high performance, on-chip DAC clock multiplier, and digital
signal processing capabilities targeted at single-band and multiband
direct to radio frequency (RF) wireless applications.
The AD9173 features three complex data input channels per RF
DAC that are bypassable. Each data input channel includes a
configurable gain stage, an interpolation filter, and a channel
numerically controlled oscillator (NCO) for flexible, multiband
frequency planning. The device supports up to a 1.54 GSPS
complex data rate per input channel and is capable of aggregating
multiple complex input data streams up to a maximum complex
data rate of 1.54 GSPS. Additionally, the AD9173 supports
ultrawide bandwidth modes bypassing the channelizers to
provide maximum data rates of up to 3.08 GSPS (with 11-bit
resolution using 16-bit serializer/deserializer (SERDES)
packing) and 3.4 GSPS (with 11-bit resolution using 12-bit
SERDES packing).
The AD9173 is available in a 144-ball BGA_ED package.
PRODUCT HIGHLIGHTS
1. Supports single-band and multiband wireless applications
with three bypassable complex data input channels per RF
DAC at a maximum complex input data rate of 1.54 GSPS
with 11-bit resolution and 1.23 GSPS with 16-bit
resolution. One independent NCO per input channel.
2. Ultrawide bandwidth channel bypass modes supporting up
to 3.08 GSPS data rates with 11-bit resolution, 16-bit
SERDES packing and 3.4 GSPS with 11-bit resolution, 12-
bit SERDES packing.
3. Low power dual converter decreases the amount of power
consumption needed in high bandwidth and multichannel
applications.
Rev. 0
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Analog Devices AD9173
AD9173
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 5
Maximum DAC Sampling Rate Specifications......................... 5
Power Supply DC Specifications ................................................ 6
Serial Port and CMOS Pin Specifications ................................. 8
Digital Input Data Timing Specifications ................................. 9
JESD204B Interface Electrical and Speed Specifications ...... 10
Input Data Rates and Signal Bandwidth Specifications ........ 10
AC Specifications........................................................................ 11
Absolute Maximum Ratings.......................................................... 13
Reflow Profile.............................................................................. 13
Thermal Characteristics ............................................................ 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 17
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Serial Port Operation ..................................................................... 27
Data Format ................................................................................ 27
Serial Port Pin Descriptions...................................................... 27
REVISION HISTORY
11/2017—Revision 0: Initial Version
Data Sheet
Serial Port Options..................................................................... 27
JESD204B Serial Data Interface.................................................... 29
JESD204B Overview .................................................................. 29
Physical Layer ............................................................................. 32
Data Link Layer .......................................................................... 34
Syncing LMFC Signals............................................................... 37
Transport Layer .......................................................................... 42
JESD204B Test Modes ............................................................... 43
JESD204B Error Monitoring..................................................... 45
Digital Datapath ............................................................................. 48
Total Datapath Interpolation .................................................... 48
Channel Digital Datapath ......................................................... 50
Main Digital Datapath ............................................................... 53
Interrupt Request Operation ........................................................ 59
Interrupt Service Routine.......................................................... 59
Applications Information .............................................................. 60
Hardware Considerations ......................................................... 60
Analog Interface Considerations.................................................. 63
DAC Input Clock Configurations............................................ 63
Clock Output Driver.................................................................. 65
Analog Outputs .......................................................................... 65
Start-Up Sequence.......................................................................... 66
Register Summary .......................................................................... 73
Register Details ............................................................................... 81
Outline Dimensions ..................................................................... 142
Ordering Guide ........................................................................ 142
Rev. 0 | Page 2 of 142



Analog Devices AD9173
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
SERDIN0±
SERDIN7±
SYNCOUT0±
SYNCOUT1±
SERDES
JESD204B
CHANNEL 0
GAIN
CHANNEL 1
GAIN
CHANNEL 2
GAIN
CHANNEL 3
GAIN
CHANNEL 4
GAIN
CHANNEL 5
GAIN
N
N
N
N
N
N
NCO
NCO
NCO
NCO
NCO
NCO
AD9173
PA PROTECT
M
RAMP
UP/DOWN
GAIN
NCO
AD9173
DAC 0
DAC0±
PA PROTECT
M
RAMP
UP/DOWN
GAIN
NCO
DAC 1
DAC1±
SYNCHRONIZATION
LOGIC
RESET
VREF
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
SPI
DAC ALIGN
DETECT
CLOCK
RECEIVER
CLOCK DIVIDER
÷1, ÷2, ÷3, ÷4
PLL
÷1, ÷2, ÷3
CLOCK
DRIVER
CLOCK
RECEIVER
Figure 1.
Rev. 0 | Page 3 of 142







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