LVDS Interface. ADS5270 Datasheet

ADS5270 Interface. Datasheet pdf. Equivalent

ADS5270 Datasheet
Recommendation ADS5270 Datasheet
Part ADS5270
Description 8-Channel/ 12-Bit/ 40MSPS ADC with Serial LVDS Interface
Feature ADS5270; ADS5270 SBAS293D − JANUARY 2004 − REVISED MAY 2004 8-Channel, 12-Bit, 40MSPS ADC with Serial LVDS .
Manufacture Burr-Brown Corporation
Datasheet
Download ADS5270 Datasheet




Burr-Brown Corporation ADS5270
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
8-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
FEATURES
D Maximum Sample Rate: 40MSPS
D 12-Bit Resolution
D No Missing Codes
D Power Dissipation: 907mW
D CMOS Technology
D Simultaneous Sample-and-Hold
D 70.5dB SNR at 10MHz IF
D Internal and External References
D 3.3V Digital/Analog Supply
D Serialized LVDS Outputs
D Integrated Frame and Synch Patterns
D MSB and LSB First Modes
D Option to Double LVDS Clock Output Currents
D Pin- and Format-Compatible Family
D TQFP-80 PowerPADPackage
APPLICATIONS
D Portable Ultrasound Systems
D Tape Drives
D Test Equipment
D Optical Networking
DESCRIPTION
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5270 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a PowerPAD TQFP-80 package and
is specified over a −40°C to +85°C operating range.
6X ADCLK
ADCLK
IN1P
IN1N
S/H
IN2P
IN2N
S/H
IN3P
IN3N
S/H
IN4P
IN4N
S/H
IN5P
IN5N
S/H
PLL
1X ADCLK
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
LCLKP
LCLKN
ADCLKP
ADCLKN
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
The ADS5270 is a high-performance, 40MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
IN6P
IN6N
S/H
IN7P
IN7N
S/H
IN8P
IN8N
S/H
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Reference
Registers
Control
INT/EXT
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
www.ti.com



Burr-Brown Corporation ADS5270
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Supply Voltage Range, LVDD . . . . . . . . . . . . . . . . . . −0.3V to 3.8V
Voltage Between AVSS and LVSS . . . . . . . . . . . . . . −0.3V to 0.3V
Voltage Between AVDD and LVDD . . . . . . . . . . . . . . −0.3V to 0.3V
Voltages Applied to External REF Pins . . . . . . . . . . −0.3V to 2.4V
All LVDS Data and Clock Outputs . . . . . . . . . . . . . . −0.3V to 2.4V
Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 2.7V
Peak Total Input Current (all inputs) . . . . . . . . . . . . . . . . . . . −30mA
Operating Free-Air Temperature Range, TA . . . . . . −40°C to 85°C
Lead Temperature 1.6mm (1/16from case for 10s) . . . . . . 220°C
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
www.ti.com
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5270
HTQFP-80(2)
PFP
−40°C to +85°C ADS5270IPFP ADS5270IPFP
Tray, 96
″ ″ ″ ″ ″ ADS5270IPFPT Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2) Thermal pad size: 4.69mm x 4.69mm (min), 6.20mm x 6.20mm (max).
RELATED PRODUCTS
MODEL
ADS5271
ADS5272
ADS5273
ADS5275
ADS5276
ADS5277
RESOLUTION (BITS)
12
12
12
10
10
10
SAMPLE RATE (MSPS)
50
65
70
40
50
65
CHANNELS
8
8
8
8
8
8
RECOMMENDED OPERATING CONDITIONS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
Low Level Voltage Clock Input
High Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
Thermal Characteristics
qJA
qJC
(1) 6 × ADCLK.
ADS5270
MIN TYP
3.0 3.3
3.0 3.3
20
VDD − 0.6
20
120
−40
21
68
MAX
3.6
3.6
40
0.6
40
240
+85
UNIT
V
V
MSPS
V
V
MHz
MHz
°C
°C/W
°C/W
REFERENCE SELECTION
MODE
2.0VPP Internal Reference
INT/EXT
1
External Reference
0
DESCRIPTION
Default with internal pull-up.
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
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Burr-Brown Corporation ADS5270
ADS5270
www.ti.com
SBAS293D − JANUARY 2004 − REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
TMIN = −40°C, and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, −1dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5270
PARAMETER
DC ACCURACY
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Offset Error(1)
Offset Temperature Coefficient
Fixed Attenuation in Channel(2)
Variable Attenuation in Channel(3)
Gain Error(4)
Gain Temperature Coefficient(5)
POWER SUPPLY
ICC Total Supply Current
I(AVDD) Analog Supply Current
I(LVDD) Digital Output Driver Supply Current
Power Dissipation
Power Down
REFERENCE VOLTAGES
VREFT
VREFB
VCM
VREFT
VREFB
Reference Top (internal)
Reference Bottom (internal)
Common-Mode Voltage
VCM Output Current(6)
Reference Top (external)
Reference Bottom (external)
External Reference Input Current(7)
ANALOG INPUT
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
Voltage Overload Recovery Time
Input Bandwidth
DIGITAL DATA OUTPUTS
Data Bit Rate
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
VIN LOW
VIN HIGH
Input Low Voltage
Input High Voltage
Input Current
Input Pin Capacitance
TEST CONDITIONS
MIN TYP MAX UNITS
fIN = 5MHz
fIN = 5MHz
REFT − REFB
−0.9
−2.0
−0.75
−2.5
Assured
±0.5
±0.6
±0.2
14
1
±0.2
±1.0
44
0.9
2.0
0.75
2.5
LSB
LSB
%FS
ppm/°C
%FS
%FS
%FS
ppm/°C
VIN = FS, FIN = 5MHz
VIN = FS, FIN = 5MHz
VIN = FS, FIN = 5MHz, LVDS Into 100Load
Clock Running
275
221
54
904 950
90
mA
mA
mA
mW
mW
±50mV Change in Voltage
1.95 2.0 2.05
0.95 1.0 1.05
1.45 1.5 1.55
±2
1.875
1.125
2.0
V
V
V
mA
V
V
mA
Differential Input Signal at 4VPP
Recovery to Within 1% of Code
−3dBFS
7.0 pF
VCM ± 0.05
V
1.5
2.02
VPP
4.0 CLK Cycles
300 MHz
240 480 MBPS
20
0 0.6
2.1 VDD
±10
5.0
MHz
V
V
µA
pF
(1) Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full scale.
(2) Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential voltage at the analog input pins are
changed from −VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code (4096LSB) by the extent of this fixed attenuation.
NOTE: VREF is defined as (REFT − REFB).
(3) Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
(4) The reference voltages are trimmed at production so that (VREFT − VREFB) is within ± 25mV of the ideal value of 1V. It does not include fixed attenuation.
(5) The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the variation of the reference voltages with
temperature.
(6) VCM provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The VCM output current specified is the additional drive of
the VCM buffer if loaded externally.
(7) Average current drawn from the reference pins in the external reference mode.
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