74HC27 Datasheet (data sheet) PDF





74HC27 Datasheet, Triple 3-input NOR gate

74HC27   74HC27  

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74HC27; 74HCT27 Triple 3-input NOR gate Rev. 5.1 — 27 November 2015 Product data sheet 1. General description The 74HC27; 74HCT27 is a triple 3-input NO R gate. Inputs include clamp diodes. Th is enables the use of current limiting resistors to interface inputs to voltag es in excess of VCC. 2. Features and be nefits  Complies with JEDEC standard no. 7A  Input levels:  For 74HC2 7: CMOS level  For 74HCT27: TTL leve l  ESD protection:  HBM JESD22-A1 14F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package opt ions  Specified from 40 C to + 85 C and from 40 C to +125  C 3. Ordering information Table 1. Ordering information

74HC27 Datasheet, Triple 3-input NOR gate

74HC27   74HC27  
Type number Package Temperature range Name Description Version 74HC27D 40 C to +125 C SO14 plastic sm all outline package; 14 leads; body wid th 3.9 mm SOT108-1 74HCT27D 74HC27DB 40 C to +125 C SSOP14 74HCT27D B plastic shrink small outline package ; 14 leads; body width SOT337-1 5.3 mm 74HC27PW 40 C to +125 C TSSOP 14 plastic thin shrink small outline pa ckage; 14 leads; body 74HCT27PW width 4.4 mm SOT402-1 74HC27BQ 40 C to +125 C 74HCT27BQ DHVQFN14 plasti c dual in-line compatible thermal enhan ced very thin quad flat package; no lea ds; 14 terminals; body 2.5  3  0. 85 mm SOT762-1 Nexperia 4. Functional diagram 74HC27; 74HCT27 Triple 3-inpu t NOR gate  $  %  &  $  %  &  $  %  & <  <  <  PQD Fig 1. Logic symbol  •      •     •    P QD Fig 2. IEC logic symbol 5. Pinn ing information 5.1 Pinning $ %< & PQ D Fig 3. Logic diagram (one gate)  $  %  $  %  &  <  *1'  + & +&7  9&&  &  <  &   %  $  < DDJ Fig 4. Pin co nfiguration SO14, (T)SSOP14 +& + &7  $  9&& WHUPLQDO LQGH[DUH D %  $  %  &  <  *1'   &  <  &  %  $ *1'  <  DDD 7UDQVSDUHQWWRSYLHZ (1) This is not a supply pin. The substrate is at








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