ą 74ACT11648 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3ĆSTATE OUTPUTS
SCAS115 − D3458, MARCH 1990 − REVISED APRIL 1993
Inputs Are TTL-Voltage Compatible
DW PACKAGE
Independent Registers A and B Buses
(TOP VIEW)
Multiplexed Real-Time and Stored Data Inverting Data Paths
G1 A1 2
28 CAB 27 SAB
Flow-Through Architecture to Optimize
A2 3
26 B1
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