SN74LS93 Datasheet: 4-BIT BINARY COUNTER





SN74LS93 4-BIT BINARY COUNTER Datasheet

Part Number SN74LS93
Description 4-BIT BINARY COUNTER
Manufacture ON Semiconductor
Total Page 7 Pages
PDF Download Download SN74LS93 Datasheet PDF

Features: SN74LS90 DECADE COUNTER; DIVIDE-BY-TWEL VE COUNTER; 4-BIT BINARY COUNTER The SN 54 / 74LS90, SN54 / 74LS92 and SN54 / 7 4LS93 are high-speed 4-bit ripple type counters partitioned into two sections. Each counter has a divide-by-two secti on and either a divide-by-five (LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transition on the clock i nputs. Each section can be used separat ely or tied together (Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-1 6 counters. All of the counters have a 2-input gated Master Reset (Clear), and the LS90 also has a 2-input gated Mast er Set (Preset 9). • Low Power Consum ption . . . Typically 45 mW • High Co unt Rates . . . Typically 42 MHz • Ch oice of Counting Modes . . . BCD, Bi-Qu inary, Divide-by-Twelve, Binary • Inp ut Clamp Diodes Limit High Speed Termin ation Effects PIN NAMES LOADING (Note a) HIGH LOW CP0 CP1 CP1 MR1, MR2 MS 1, MS2 Q0 Q1, Q2, Q3 Clock (Active LOW going edge) Input to ÷2 Section.

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SN74LS90
DECADE COUNTER;
DIVIDE-BY-TWELVE
COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are
high-speed 4-bit ripple type counters partitioned into two sections.
Each counter has a divide-by-two section and either a divide-by-five
(LS90), divide-by-six (LS92) or divide-by-eight (LS93) section which
are triggered by a HIGH-to-LOW transition on the clock inputs. Each
section can be used separately or tied together (Q to CP) to form BCD,
bi-quinary, modulo-12, or modulo-16 counters. All of the counters
have a 2-input gated Master Reset (Clear), and the LS90 also has a
2-input gated Master Set (Preset 9).
Low Power Consumption . . . Typically 45 mW
High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING (Note a)
HIGH
LOW
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
÷2 Section
Clock (Active LOW going edge) Input to
÷5 Section (LS90), ÷6 Section (LS92)
Clock (Active LOW going edge) Input to
÷8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from ÷2 Section (Notes b & c)
Outputs from ÷5 (LS90), ÷6 (LS92),
÷8 (LS93) Sections (Note b)
0.5 U.L.
1.5 U.L.
0.5 U.L.
2.0 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b. Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
6 7 LOGIC SYMBOL
http://onsemi.com
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
14
1
J SUFFIX
CERAMIC
CASE 632-08
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
1 2 LS90
LS92
LS93
MS
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
14 CP0
1 CP1
MR Q0 Q1 Q2 Q3
12 12
12
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
6 7 12 11 9 8
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
© Semiconductor Components Industries, LLC, 2006
July, 2006 Rev. 6
1
Publication Order Number:
SN74LS90/D

                    






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