SN74ABT3612 Datasheet | BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY





(Datasheet) SN74ABT3612 Datasheet PDF Download

Part Number SN74ABT3612
Description BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
Manufacture etcTI
Total Page 30 Pages
PDF Download Download SN74ABT3612 Datasheet PDF

Features: SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRE CTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS 129G – JULY 1992 – REVISED APRIL 19 98 D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident D Two Indep endent 64 × 36 Clocked FIFOs Buffering Data in Opposite Directions D Mailbox- Bypass Register for Each FIFO D Program mable Almost-Full and Almost-Empty Flag s D Microprocessor Interface Control Lo gic D EFA, FFA, AEA, and AFA Flags Sync hronized by CLKA D EFB, FFB, AEB, and AFB Flags Synchronized by CLKB D Passiv e Parity Checking on Each Port D Parity Generation Can Be Selected for Each Po rt D Low-Power Advanced BiCMOS Technolo gy D Supports Clock Frequencies up to 6 7 MHz D Fast Access Times of 10 ns D Pa ckage Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Fl at (PQ) Packages description The SN74A BT3612 is a high-speed, low-power BiCMO S bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MH z and has read access times as fast as 10 ns. Two independent 64 × 36 .

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SN74ABT3612
64 × 36 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS129G – JULY 1992 – REVISED APRIL 1998
D Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D Two Independent 64 × 36 Clocked FIFOs
Buffering Data in Opposite Directions
D Mailbox-Bypass Register for Each FIFO
D Programmable Almost-Full and
Almost-Empty Flags
D Microprocessor Interface Control Logic
D EFA, FFA, AEA, and AFA Flags
Synchronized by CLKA
D EFB, FFB, AEB, and AFB Flags
Synchronized by CLKB
D Passive Parity Checking on Each Port
D Parity Generation Can Be Selected for Each
Port
D Low-Power Advanced BiCMOS Technology
D Supports Clock Frequencies up to 67 MHz
D Fast Access Times of 10 ns
D Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM
FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions
and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is
stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers.
Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each
port and can be ignored if not desired. Parity generation can be selected for data read from each port. Two or
more devices can be used in parallel to create wider datapaths.
The SN74ABT3612 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FFA, FFB) and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock
that writes data to its array. The empty flag (EFA, EFB) and almost-empty (AEA, AEB) flag of a FIFO are
two-stage synchronized to the port clock that reads data from its array.
The SN74ABT3612 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
D FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number
SCAA007)
D Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
D Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1998, Texas Instruments Incorporated
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