D Qualified for Automotive Applications
D ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
Using Machine Model (C = 200 pF, R = 0)
D Inputs Are TTL-Voltage Compatible
D Latch-Up Performance Exceeds 250 mA Per
OCTAL TRANSPARENT DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCLS541A − SEPTEMBER 2003 − REVISED APRIL 2008
The SN74AHCT573 is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
−40°C to 125°C SOIC − DW
Tape and reel SN74AHCT573QDWRQ1 AHCT573QQ1
† For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
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testing of all parameters.
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