TMS29F008T Datasheet: FLASH MEMORIES





TMS29F008T Datasheet PDF

Part Number TMS29F008T
Description FLASH MEMORIES
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS29F008T Datasheet PDF

Features: "D Single Power Supply Supports 5 V 10% Read/Write Operation D Organization . . . 1 048576 By 8 Bits D Array-Blocking Architecture – One 16K-Byte Boot Sect or – Two 8K-Byte Parameter Sectors One 32K-Byte Sector – Fifteen 64K-B yte Sectors – Any Combination of Sect ors Can Be Erased. Supports Full-Chip E rase – Any Combination of Sectors Can Be Marked as Read-Only D Boot-Code Sec tor Architecture – T = Top Sector – B = Bottom Sector D Sector Protection – Hardware Protection Method That Dis ables Any Combination of Sectors From W rite or Erase Operations Using Standard Programming Equipment D Embedded Progr am/Erase Algorithms – Automatically P re-Programs and Erases Any Sector – A utomatically Programs and Verifies the Program Data at Specified Address D JED EC Standards – Compatible With JEDEC Byte Pinouts – Compatible With JEDEC EEPROM Command Set D Fully Automated On -Chip Erase and Program Operations D 10 0 000 Program/Erase Cycles D Low Power Dissipation – 40-mA Typical Active Read for Byte M.

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TMS29F008T datasheet
"D Single Power Supply Supports 5 V 10%
Read/Write Operation
D Organization . . . 1 048576 By 8 Bits
D Array-Blocking Architecture
– One 16K-Byte Boot Sector
– Two 8K-Byte Parameter Sectors
– One 32K-Byte Sector
– Fifteen 64K-Byte Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
D Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
D Sector Protection
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
D Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
D JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
D Fully Automated On-Chip Erase and
Program Operations
D 100 000 Program/Erase Cycles
D Low Power Dissipation
– 40-mA Typical Active Read for Byte Mode
– 60-mA Typical Program/Erase Current
– Less Than 100-µA Standby Current
– 5 µA in Deep Power-Down Mode
TMS29F008T, TMS29F008B
1048576 BY 8-BIT
FLASH MEMORIES
SMJS845A – MARCH 1997 – REVISED OCTOBER 1997
D All Inputs/Outputs TTL-Compatible
D Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
D Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
D 40-Pin Thin Small-Outline Package (TSOP)
(DCD Suffix)
D Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
– Hardware Method for Detection of
Program/Erase Cycle Completion
Through Ready/Busy (RY/BY) Output Pin
"D High-Speed Data Access at 5-V VCC 10%
at Three Temperature Ranges
– 80 ns Commercial . . . 0°C to 70°C
– 90 ns Commercial . . . 0°C to 70°C
– 100 ns Extended . . . –40°C to 85°C
– 120 ns Automotive . . . –40°C to 125°C
A[0 :19]
DQ[0 :7]
CE
OE
NC
RESET
RY / BY
VCC
VSS
WE
PIN NOMENCLATURE
Address Inputs
Data In / Data out
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Ready / Busy Output
Power Supply
Ground
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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