Timer. TLC555M Datasheet

TLC555M Datasheet PDF


Part

TLC555M

Description

Timer

Manufacture

etcTI

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TLC555M Datasheet
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TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
TLC555 LinCMOS™ Timer
1 Features
1 Very low power consumption:
– 1-mW typical at VDD = 5 V
• Capable of operation in astable mode
• CMOS output capable of swinging rail to rail
• High output current capability
– Sink: 100-mA typical
– Source: 10-mA typical
• Output fully compatible with CMOS, TTL, and
MOS
• Low supply current reduces spikes during output
transitions
• Single-supply operation from 2 V to 15 V
• Functionally interchangeable with the NE555; has
same pinout
• ESD protection exceeds 2000 V per MIL-STD-
883C, method 3015.2
• Available in Q-temp automotive
– High-reliability automotive applications
– Configuration control and print support
– Qualification to automotive standards
2 Applications
• Precision timing
• Pulse generation
• Sequential timing
• Time delay generation
• Pulse width modulation
• Pulse position modulation
• Linear ramp generator
3 Description
The TLC555 is a monolithic timing circuit fabricated
using the TI LinCMOS™ process. The timer is fully
compatible with CMOS, TTL, and MOS logic and
operates at frequencies up to 2 MHz. Because of its
high input impedance, this device supports smaller
timing capacitors than those supported by the NE555
or LM555. As a result, more accurate time delays and
oscillations are possible. Power consumption is low
across the full range of power-supply voltage.
Like the NE555, the TLC555 has a trigger level equal
to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of
the supply voltage. These levels can be altered by
use of the control voltage terminal (CONT). When the
trigger input (TRIG) falls below the trigger level, the
flip-flop is set and the output goes high. If TRIG is
above the trigger level and the threshold input
(THRES) is above the threshold level, the flip-flop is
reset and the output is low. The reset input (RESET)
can override all other inputs and can be used to
initiate a new timing cycle. If RESET is low, the flip-
flop is reset and the output is low. Whenever the
output is low, a low-impedance path is provided
between the discharge terminal (DISCH) and GND.
All unused inputs must be tied to an appropriate logic
level to prevent false triggering.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
TLC555C
PDIP (8)
SOP (8)
9.81 mm × 6.38 mm
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
TLC555I
SOIC (8)
PDIP (8)
4.90 mm × 3.91 mm
9.81 mm × 6.38 mm
TLC555M
LCCC (20)
CDIP (8)
8.89 mm × 8.89 mm
9.60 mm × 6.67 mm
TLC555Q
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
6
THRES
Simplified Schematic
CONT
5
VDD
8
RESET
4
R
R1
R1
S
R
3
OUT
2
TRIG
R
1
GND
7
DISCH
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC555M Datasheet
TLC555
SLFS043I – SEPTEMBER 1983 – REVISED JULY 2019
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 Recommended Operating Conditions....................... 6
6.3 Thermal Information .................................................. 6
6.4 Electrical Characteristics: VDD = 2 V for TLC555C,
VDD = 3 V for TLC555I ............................................... 7
6.5 Electrical Characteristics: VDD = 5 V......................... 8
6.6 Electrical Characteristics: VDD = 15 V....................... 9
6.7 Operating Characteristics........................................ 11
6.8 Typical Characteristics ............................................ 12
7 Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 19
8 Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Applications ................................................ 20
9 Power Supply Recommendations...................... 26
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 27
11 Device and Documentation Support ................. 28
11.1 Receiving Notification of Documentation Updates 28
11.2 Community Resources.......................................... 28
11.3 Trademarks ........................................................... 28
11.4 Electrostatic Discharge Caution ............................ 28
11.5 Glossary ................................................................ 28
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision H (August 2016) to Revision I
Page
• Added MIN value for input voltage in Absolute Maximum Ratings ........................................................................................ 6
• Added discharge pin in Absolute Maximum Ratings .............................................................................................................. 6
• Changed MIN supply voltage based on part number in Recommended Operating Conditions............................................. 6
• Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I .................................................................................................................................................................................. 7
• Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 5 V ..................................................... 8
• Changed VOH test condition current to –1 mA in Electrical Characteristics: VDD = 5 V.......................................................... 8
• Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 5 V .................................................... 9
• Added trigger, threshold capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................... 9
• Added power dissipation capacitance TYP value in Electrical Characteristics: VDD = 15 V ................................................ 10
• Added Operating Characteristics to the Specifications section............................................................................................ 11
• Added Supply Current vs Supply Voltage chart to the Typical Characteristics section ....................................................... 12
• Added Control Impedance vs Temperature chart to the Typical Characteristics section .................................................... 12
• Added Output Low Resistance vs Temperature chart to the Typical Characteristics section.............................................. 12
• Added Output High Resistance vs Temperature chart to the Typical Characteristics section............................................. 12
• Added Propagation Delay vs Control Voltage chart, VDD = 2 V to the Typical Characteristics section ............................... 12
• Added Propagation Delay vs Control Voltage chart, VDD = 5 V to the Typical Characteristics section ............................... 12
• Changed trigger high hold time to 1 µs in the Monostable Operation section ..................................................................... 15
• Changed minimum monostable pulse width to 1 µs in the Monostable Operation section.................................................. 15
• Changed Output Pulse Duration vs Capacitance chart scale down to 0.001 ms in the Monostable Operation section...... 15
• Added more astable frequency formulas to the Astable Operation section ......................................................................... 17
• Changed scale on Free-Running Frequency vs Timing Capacitance chart up to 2 MHz in the Astable Operation section 18
• Added CONT pin table note to the Function Table in the Device Functional Modes section .............................................. 19
• Changed the application curve chart in the Pulse-Width Modulation section ...................................................................... 22
• Changed the application curve charts in the Pulse-Position Modulation section ................................................................. 23
• Added clamping diodes to Sequential Timer Circuit in the Sequential Timer section.......................................................... 24
2 Submit Documentation Feedback
Product Folder Links: TLC555
Copyright © 1983–2019, Texas Instruments Incorporated


Features Datasheet pdf Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity Reference Design TLC555 SLFS04 3I – SEPTEMBER 1983 – REVISED JULY 2019 TLC555 LinCMOS™ Timer 1 Feature s •1 Very low power consumption: – 1-mW typical at VDD = 5 V • Capable o f operation in astable mode • CMOS ou tput capable of swinging rail to rail High output current capability – S ink: 100-mA typical – Source: 10-mA t ypical • Output fully compatible with CMOS, TTL, and MOS • Low supply curr ent reduces spikes during output transi tions • Single-supply operation from 2 V to 15 V • Functionally interchang eable with the NE555; has same pinout ESD protection exceeds 2000 V per MI L-STD883C, method 3015.2 • Available in Q-temp automotive – High-reliabili ty automotive applications – Configur ation control and print support – Qua lification to automotive standards 2 Ap plications • Precision timing • Pul se generation • Sequential timing • Time delay generation • Pulse width modulation • Pulse position modul.
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