TLC552C Datasheet PDF


Part Number

TLC552C

Description

DUAL TIMER

Manufacture

etcTI

Total Page 13 Pages
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Features Datasheet pdf TLC552C DUAL LINCMOS™ TIMER D Very Lo w Power Consumption . . . 2 mW Typ at V DD = 5 V D Capable of Operation in Asta ble Mode D CMOS Output Capable of Swing ing Rail to Rail D High Output-Current Capability Sink 100 mA Typ Source 10 mA Typ D Output Fully Compatible With CMO S, TTL, and MOS D Low Supply Current Re duces Spikes During Output Transitions D High-Impedance Inputs . . . 1012 Ω Typ D Single-Supply Operation From 1 V to 18 V D Functionally Interchangeable With the NE556; Has Same Pinout descrip tion The TLC552 is a dual monolithic ti ming circuit fabricated using TI LinCMO S™ process, which provides full compa tibility with CMOS, TTL, and MOS logic and operation at frequencies up to 2 MHz. .
Keywords TLC552C, datasheet, pdf, etcTI, DUAL, TIMER, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

TLC552C Datasheet
TLC552C
DUAL LINCMOSTIMER
D Very Low Power Consumption . . . 2 mW
Typ at VDD = 5 V
D Capable of Operation in Astable Mode
D CMOS Output Capable of Swinging Rail to
Rail
D High Output-Current Capability
Sink 100 mA Typ
Source 10 mA Typ
D Output Fully Compatible With CMOS, TTL,
and MOS
D Low Supply Current Reduces Spikes
During Output Transitions
D High-Impedance Inputs . . . 1012 Typ
D Single-Supply Operation From 1 V to 18 V
D Functionally Interchangeable With the
NE556; Has Same Pinout
description
The TLC552 is a dual monolithic timing circuit
fabricated using TI LinCMOSprocess, which
provides full compatibility with CMOS, TTL, and
MOS logic and operation at frequencies up to
2 MHz. Accurate time delays and oscillations are
possible with smaller, less-expensive timing
capacitors than the NE555 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
TIMER
#1
SLFS046 – FEBRUARY 1984 – REVISED MAY 1988
D OR N PACKAGE
(TOP VIEW)
DSCH
THRES
CONT
RESET
OUT
TRIG
GND
1
2
3
4
5
6
7
14 VDD
13 DSCH
12 THRES
11 CONT
10 RESET
9 OUT
8 TRIG
TIMER
#2
functional block diagram (each timer)
VDD
CONT
R
THRES
R
RESET
R1
R
S
1
OUT
TRIG
R
GND
RESET can override TRIG and THRES.
TRIG can override THRES.
DSCH
Like the NE556, the TLC552 has a trigger level
approximately one-third of the supply voltage and
a threshold level approximately two-thirds of the
supply voltage. These levels can be altered by use
of the control voltage terminal. When the trigger
AVAILABLE OPTIONS
SYMBOLIZATION
DEVICE PACKAGE
SUFFIX
OPERATING
TEMPERATURE
RANGE
VT max
at 25°C
input falls below the trigger level, the flip-flop is set
TLC552C
D,N
0°C to 70°C
3.8 mV
and the output goes high. If the trigger input is
above the trigger level and the threshold input is
The D packages are available taped and reeled. Add the suffix R
to the device type when ordering (i.e., TLC552CDR).
above the threshold level, the flip-flop is reset and
the output is low. The reset input can override all other inputs and can be used to initiate a new
timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC552 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
1




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