REGISTERS. SN54HC166 Datasheet

SN54HC166 Datasheet PDF


Part

SN54HC166

Description

8-BIT PARALLEL-LOAD SHIFT REGISTERS

Manufacture

etcTI

Page 30 Pages
Datasheet
Download SN54HC166 Datasheet


SN54HC166 Datasheet
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 80-µA Max ICC
D Typical tpd = 13 ns
D ±4-mA Output Drive at 5 V
SN54HC166 . . . J OR W PACKAGE
SN74HC166 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
SER
A
B
C
D
CLK INH
CLK
GND
1
2
3
4
5
6
7
8
16 VCC
15 SH/LD
14 H
13 QH
12 G
11 F
10 E
9 CLR
SN54HC166, SN74HC166
8ĆBIT PARALLELĆLOAD SHIFT REGISTERS
SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003
D Low Input Current of 1 µA Max
D Synchronous Load
D Direct Overriding Clear
D Parallel-to-Serial Conversion
SN54HC166 . . . FK PACKAGE
(TOP VIEW)
B
C
NC
D
CLK INH
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
H
QH
NC
G
F
description/ordering information
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC166N
SN74HC166N
Tube of 40
SN74HC166D
SOIC − D
Reel of 2500
Reel of 250
SN74HC166DR
SN74HC166DT
HC166
−40°C to 85°C
SOP − NS
SSOP − DB
Reel of 2000
Reel of 2000
SN74HC166NSR
SN74HC166DBR
HC166
HC166
Tube of 90
SN74HC166PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC166PWR
SN74HC166PWT
HC166
CDIP − J
Tube of 25
SNJ54HC166J
SNJ54HC166J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC166W
SNJ54HC166W
LCCC − FK
Tube of 55
SNJ54HC166FK
SNJ54HC166FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54HC166 Datasheet
SN54HC166, SN74HC166
8ĆBIT PARALLELĆLOAD SHIFT REGISTERS
SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding
clear (CLR) input. The parallel-in or serial-in modes are established by the shift/ load (SH/LD) input. When high,
SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock
(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on
the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
CLR
L
H
H
H
H
H
FUNCTION TABLE
INPUTS
SH/LD CLK INH CLK
X XX
X LL
L L
H L
H L
X H
SER
X
X
X
H
L
X
PARALLEL
A...H
X
X
a...h
X
X
X
OUTPUTS
INTERNAL
QA QB QH
L
QA0
a
H
L
QA0
L
QB0
b
QAn
QAn
QB0
L
QH0
h
QGn
QGn
QH0
logic diagram (positive logic)
15
SH/LD
A BC DE F GH
2 3 4 5 10 11 12 14
1
SER
CLK INH
6
7
CLK
9
CLR
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
13
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
QH
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features Datasheet pdf D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 80-µA Max ICC D Typical tpd = 13 ns D ±4-mA Output Drive at 5 V SN54HC166 . . . J O R W PACKAGE SN74HC166 . . . D, DB, N, N S, OR PW PACKAGE (TOP VIEW) SER A B C D CLK INH CLK GND 1 2 3 4 5 6 7 8 16 VCC 15 SH/LD 14 H 13 QH 12 G 11 F 10 E 9 CLR SN54HC166, SN74HC166 8ĆBIT PARA LLELĆLOAD SHIFT REGISTERS SCLS117D − DECEMBER 1982 − REVISED SEPTEMBER 20 03 D Low Input Current of 1 µA Max D S ynchronous Load D Direct Overriding Cle ar D Parallel-to-Serial Conversion SN54 HC166 . . . FK PACKAGE (TOP VIEW) A SE R NC VCC SH/LD B C NC D CLK INH 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 H QH NC G F CLK GND NC CLR E description/ordering information NC No internal connection ORDERING INFO RMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC166N SN74HC166N Tub e of 40 SN74HC166D SOIC − D Reel of 2500 Reel of 250 SN74HC166DR SN74HC166.
Keywords SN54HC166, datasheet, pdf, etcTI, 8-BIT, PARALLEL-LOAD, SHIFT, REGISTERS, N54HC166, 54HC166, 4HC166, SN54HC16, SN54HC1, SN54HC, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)