74LS90 COUNTER Datasheet

74LS90 Datasheet PDF, Equivalent


Part Number

74LS90

Description

DECADE COUNTER

Manufacture

ETC

Total Page 3 Pages
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Download 74LS90 Datasheet PDF


74LS90
54/7490A
54LS/74LS90
DECADE COUNTER
90
CONNECTION DIAGRAM
PINOUT A
DESCRIPTION — The ’90 is a 4-stage ripple counter containing a high speed
flip-flop acting as a divide-by-two and three flip-flops connected as a divide-
by-five counter. It can be connected to operate with a conventional BCD out­
put pattern or it can be connected to provide a 50% duty cycle output. In the
BCD mode, HIGH signals on the Master Set (MS) inputs set the outputs to
BCD nine. HIGH signals on the Master Reset (MR) inputs force all outputs
LOW. For a similar counter with corner power pins, see the ’LS290; for dual
versions, see the ’LS390 and ’LS490.
ORDERING CODE: See Section 9
PKGS
PIN
OUT
COMMERCIAL GRADE
Vcc = +5.0 V ±5%,
T a = 0°C to +70°C
MILITARY GRADE
Vcc = +5.0 V ±10%,
TA = -55° C to +125° C
Plastic
DIP (P)
A 7490APC, 74LS90PC
Ceramic
DIP (D)
A 7490ADC, 74LS90DC 5490ADM, 54LS90DM
Flatpak
(F)
A 7490AFC, 74LS90FC
5490AFM, 54LS90FM
PKG
TYPE
9A
6A
3I
LOGIC SYMBOL
67
Vcc = Pin 5
GND = Pin 10
NC = Pins 4,13
INPUT LOADING/FAN-OUT: See Section 3 for U.L. defintions
PIN NAMES
DESCRIPTION
CPo
CPi
MRi, MR2
MSi , MS2
Qo
+2 Section Clock Input
(Active Falling Edge)
-H5 Section Clock Input
(Active Falling Edge)
Asynchronous Master Reset Inputs
(Active HIGH)
Asynchronous Master Set
(Preset 9) Inputs (Active HIGH)
-j-2 Section Output*
-^-5 Section Outputs
*The Qo output is guaranteed to drive the full rated fan-out plus the C P i input.
54/74 (U.L.)
HIGH/LOW
2.0/2.0
3.0/3.0
1.0/1.0
1.0/1.0
20/10
20/10
54/74LS (U.L.)
HIGH/LOW
0.125/1.5
0.250/2.0
0.5/0.25
0.5/0.25
10/5.0
(2.5)
10/5.0
(2.5)

74LS90
90
FUNCTIONAL DESCRIPTION— The ’90 is a 4-bit ripple type decade counter. It consists of four master/slave
flip-flops which are internally connected to provide a divide-by-two section and a divide-by-five section. Each
section has a separate clock input which initiates state changes of the counter on the HIGH-to-LOW clock
transition. State changes of the Q outputs do not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding spikes and should not beused forelocks or strobes.
The Qo output of each device is designed and specified to drive the rated fan-out plus the CPi input. A gated
AND asynchronous Master Reset (MRi, MR2) is provided which overrides the clocks and resets (clears) all the
flip-flops. A gated AN D asynchronous Master Set (MS1, MS2) is provided which overrides the clocks and the MR
inputs and sets the outputs to nine (HLLH). Since the output from the divide-by-two section is not internally
connected to the succeeding stages, the devices may be operated in various counting modes.:
A. BCD Decade (8421) Counter — The CP1 input must be externally connected to the Qo output. The CPo
input receives the incoming count and a BCD count sequence is produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3 output must be externally connected to the
CPo input. The input count is then applied to the CP1 input and a divide-by-ten square wave is obtained at
output Qo.
C. Divide-By-Two and Divide-By-Five Counter — No external interconnections are required. The first
flip-flop is used as a binary element for the divide-by-two function (CPo as the input and Qo as the output).
The CP1 input is used to obtain binary divide-by-five operation at the Q3 output.
MODE SELECTION
RESET/SET INPUTS
OUTPUTS
MR1 MR2 MS1 MS2 Qo Q1 Q3 Q3
HH L X LLLL
HH X L LLLL
X X H H HL L H
LX L X
XL X L
LX X L
XL L X
Count
Count
Count
Count
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
LOGIC DIAGRAM
MR1
MR2
BCD COUNT SEQUENCE
COUNT
OUTPUTS
Qo Q1 Q2 Q*3
0 LLLL
1 HL L L
2 L HL L
3 HHL L
4 L L HL
5 HL HL
6 L HHL
7 HHHL
8 LLLH
9 HL L H
NOTE: Output Qo is connected
to Input CP1 for B CD count.
CPo
CP1
MR1
MR2
Qo Q1 Q2
Q3


Features 54/7490A 54LS/74LS90 DECADE COUNTER 90 CONNECTION DIAGRAM PINOUT A DESCRIPTIO N — The ’90 is a 4-stage ripple cou nter containing a high speed flip-flop acting as a divide-by-two and three fli p-flops connected as a divideby-five co unter. It can be connected to operate w ith a conventional BCD out­ put patter n or it can be connected to provide a 5 0% duty cycle output. In the BCD mode, HIGH signals on the Master Set (MS) inp uts set the outputs to BCD nine. HIGH s ignals on the Master Reset (MR) inputs force all outputs LOW. For a similar co unter with corner power pins, see the LS290; for dual versions, see the ’ LS390 and ’LS490. ORDERING CODE: See Section 9 PKGS PIN OUT COMMERCIAL G RADE Vcc = +5.0 V ±5%, T a = 0°C to + 70°C MILITARY GRADE Vcc = +5.0 V ±10 %, TA = -55° C to +125° C Plastic DI P (P) A 7490APC, 74LS90PC Ceramic DIP (D) A 7490ADC, 74LS90DC 5490ADM, 54LS 90DM Flatpak (F) A 7490AFC, 74LS90FC 5490AFM, 54LS90FM PKG TYPE 9A 6A 3I LOGIC SYMBOL 67 Vcc = Pin 5 GND = Pin 10 .
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