AD14160 Multiprocessor Datasheet

AD14160 Datasheet PDF, Equivalent


Part Number

AD14160

Description

DSP Multiprocessor

Manufacture

Analog Devices

Total Page 30 Pages
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AD14160
a
Quad-SHARC®
DSP Multiprocessor Family
AD14160/AD14160L
PERFORMANCE FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADSP-21060 Core Processor (. . . ؋4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction Execution–Each of Four Processors
ID2-0
CPA
LINK 0
LINK 0
ID2-0
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
SPORT 1
SPORT 0 SHARC_A
TDI
LINK 5
TDO
LINK 5
TDI
CPA
SHARC_B SPORT 1
SPORT 0
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two
from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
O32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
BOn-Chip Emulation
SPACKAGING FEATURES
452-Lead Ceramic Ball Grid Array (CBGA)
O1.85" (47 mm) Body Size
0.200" Max Height
L0.050" Ball Pitch
E29 Grams (typical)
TEJC = 0.36؇C/W
AD14160/
AD14160L
SHARC BUS (ADDR31-0, DATA47-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR6-1, RPBA, DMAR1.2, DMAG1.2)
ID2-0
CPA SHARC_D
SPORT 1
SPORT 0
TDO
LINK 0
LINK 5
TDI
LINK 0 SHARC_C
LINK 5
TDO
ID2-0
CPA
SPORT 1
SPORT 0
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi-
processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance—density and lowest
cost— performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.
The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
s
s
s
s
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998

AD14160
AD14160/AD14160L
DETAILED DESCRIPTION
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
Architectural Features
SHARC’s core also implements two data address generators
ADSP-21060 Core
(DAGs), implementing circular data buffers in hardware. The
The AD14160/AD14160L is based on the powerful ADSP-21060 DAGs contain sufficient registers to allow the creation of up to
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
32 circular buffers. The 48-bit instruction word accommodates a
high performance floating-point DSP core with integrated, on- variety of parallel operations, for concise programming. For ex-
chip system features including a 4 Mbit SRAM memory, host
ample, the ADSP-21060 can conditionally execute a multiply, an
processor interface, DMA controller, serial ports, and both link add, a subtract, and a branch, all in a single instruction.
port and parallel bus connectivity for glueless DSP multiprocess- The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
ing, (see Figure 1). It is fabricated in a high speed, low power
nized as two blocks of 2 Mbits, which can be configured for
CMOS process, and has a 25 ns instruction cycle time. The arith- different combinations of code and data storage. The memory
metic/ logic unit (ALU), multiplier and shifter all perform single- can be configured as a maximum of 128K words of 32-bit data,
cycle instructions, and the three units are arranged in parallel,
256K words of 16-bit data, 80K words of 48-bit instructions (or
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
OPM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
Bing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
SOCORE PROCESSOR
LTIMER INSTRUCTION
CACHE
32 x 48-BIT
ETEDAG1 DAG2
PROGRAM
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
JTAG
TEST AND
EMULATION
7
8 x 4 x 32 8 x 4 x 24
SEQUENCER
EXTERNAL
PM ADDRESS BUS
24
IOD IOA
48 17
PORT
DM ADDRESS BUS 32
ADDR BUS
MUX
32
BUS
CONNECT
(PX)
PM DATA BUS 48
DM DATA BUS 40/32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
I/O PROCESSOR
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)
–2– REV. A


Features a Quad-SHARC® DSP Multiprocessor Famil y AD14160/AD14160L PERFORMANCE FEATUR ES FUNCTIONAL BLOCK DIAGRAM ADSP-2106 0 Core Processor (. . . ؋4) 480 MFLOP S Peak, 320 MFLOPS Sustained CS TIMEXP LINK 1 LINK 2 LINK 3 LINK 4 IRQ2-0 FLA G3-0 CS TIMEXP LINK 1 LINK 2 LINK 3 LI NK 4 IRQ2-0 FLAG3-0 25 ns Instruction Rate, Single-Cycle Instruction Executio n–Each of Four Processors ID2-0 CPA LINK 0 LINK 0 ID2-0 EBOOT, LBOOT, B MS EMU CLKIN RESET TCK, TMS, TRST EBOO T, LBOOT, BMS EMU CLKIN RESET TCK, TMS, TRST 16 Mbit Shared SRAM (Internal to SHARCs) 4 Gigawords Addressable Off-Mo dule Memory SPORT 1 SPORT 0 SHARC_A TD I LINK 5 TDO LINK 5 TDI CPA SHARC_B SPORT 1 SPORT 0 Sixteen 40 Mbyte/s Lin k Ports (Four per SHARC) Eight 40 Mbit/ s Independent Serial Ports (Two from Ea ch SHARC) 5 V and 3.3 V Operation 32-Bi t Single Precision and 40-Bit Extended Precision IEEE Floating Point Data Form ats, or O32-Bit Fixed Point Data Format IEEE JTAG Standard 1149.1 Test Access Port and BOn-Chip Emulation .
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