Spartan-II FPGA. XC2S200 Datasheet

XC2S200 FPGA. Datasheet pdf. Equivalent

XC2S200 Datasheet
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Part XC2S200
Description Spartan-II FPGA
Feature XC2S200; R Spartan-II FPGA Family Data Sheet DS001 June 13, 2008 Product Specification This document inclu.
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Xilinx XC2S200
R Spartan-II FPGA Family
Data Sheet
DS001 June 13, 2008
Product Specification
This document includes all four modules of the Spartan®-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
• Introduction
• Features
• General Overview
• Product Availability
• User I/O Chart
• Ordering Information
Module 2:
Functional Description
DS001-2 (v2.8) June 13, 2008
• Architectural Description
- Spartan-II Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
• Development System
• Configuration
- Configuration Timing
• Design Considerations
Module 3:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
• DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
• Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
Module 4:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
• Pin Definitions
• Pinout Tables
IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001 June 13, 2008
Product Specification
www.xilinx.com
1



Xilinx XC2S200
6
R
DS001-1 (v2.8) June 13, 2008
0
Introduction
The Spartan®-II Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
Features
• Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex® FPGA
architecture
- Unlimited reprogrammability
- Very low cost
- Cost-effective 0.18 micron process
Spartan-II FPGA Family:
Introduction and Ordering
Information
Product Specification
• System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
• Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
• Fully supported by powerful Xilinx® ISE® development
system
- Fully automatic mapping, placement, and routing
Table 1: Spartan-II FPGA Family Members
Device
Logic
Cells
System Gates
(Logic and RAM)
CLB
Array
(R x C)
Total
CLBs
Maximum
Available
User I/O(1)
Total
Distributed RAM
Bits
XC2S15
432
15,000
8 x 12
96
86
6,144
XC2S30
972
30,000
12 x 18 216
92
13,824
XC2S50
1,728
50,000
16 x 24 384
176
24,576
XC2S100 2,700
100,000
20 x 30 600
176
38,400
XC2S150 3,888
150,000
24 x 36 864
260
55,296
XC2S200 5,292
200,000
28 x 42 1,176
284
75,264
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 2, page 4.
Total
Block RAM
Bits
16K
24K
32K
40K
48K
56K
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
2



Xilinx XC2S200
R Spartan-II FPGA Family: Introduction and Ordering Information
General Overview
The Spartan-II family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited
reprogramming cycles are possible with this approach.
Stored values in these cells determine logic functions and
interconnections implemented in the FPGA. Configuration
data can be read from an external serial PROM (master
serial mode), or written into the FPGA in slave serial, slave
parallel, or Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume
applications where the versatility of a fast programmable
solution adds benefits. Spartan-II FPGAs are ideal for
shortening product development cycles while offering a
cost-effective solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and
semiconductor technology. Spartan-II devices provide
system clock rates up to 200 MHz. In addition to the
conventional benefits of high-volume programmable logic
solutions, Spartan-II FPGAs also offer on-chip synchronous
single-port and dual-port RAM (block and distributed form),
DLL clock drivers, programmable set and reset on all
flip-flops, fast carry logic, and many other features.
DLL
CLBs
CLBs
DLL
CLBs
CLBs
DLL DLL
I/O LOGIC
XC2S15
Figure 1: Basic Spartan-II Family FPGA Block Diagram
DS001_01_091800
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
3





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