BUFFER GATES. SN54AHCT125 Datasheet

SN54AHCT125 GATES. Datasheet pdf. Equivalent

SN54AHCT125 Datasheet
Recommendation SN54AHCT125 Datasheet
Part SN54AHCT125
Description QUADRUPLE BUS BUFFER GATES
Feature SN54AHCT125; D Inputs Are TTL-Voltage Compatible D Latch-Up Performance Exceeds 250 mA Per JESD 17 SN54AHCT125, .
Manufacture etcTI
Datasheet
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Texas Instruments SN54AHCT125
D Inputs Are TTL-Voltage Compatible
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54AHCT125 . . . J OR W PACKAGE
SN74AHCT125 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN74AHCT125 . . . RGY PACKAGE
(TOP VIEW)
1A
1Y
2OE
2A
2Y
2
3
4
5
6
1
7
14
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8
SN54AHCT125 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2OE
NC
2A
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
4A
NC
4Y
NC
3OE
description/ordering information
NC − No internal connection
The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Tape and reel SN74AHCT125RGYR HB125
PDIP − N
Tube
SN74AHCT125N
SN74AHCT125N
−40°C to 85°C
SOIC − D
SOP − NS
SSOP − DB
Tube
Tape and reel
Tape and reel
Tape and reel
SN74AHCT125D
SN74AHCT125DR
SN74AHCT125NSR
SN74AHCT125DBR
AHCT125
AHCT125
HB125
TSSOP − PW
TVSOP − DGV
Tube
Tape and reel
Tape and reel
SN74AHCT125PW
SN74AHCT125PWR
SN74AHCT125DGVR
HB125
HB125
CDIP − J
Tube
SNJ54AHCT125J
SNJ54AHCT125J
−55°C to 125°C CFP − W
Tube
SNJ54AHCT125W
SNJ54AHCT125W
LCCC − FK
Tube
SNJ54AHCT125FK
SNJ54AHCT125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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Texas Instruments SN54AHCT125
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003
FUNCTION TABLE
(each buffer)
INPUTS
OE A
OUTPUT
Y
LH
H
LL
L
HX
Z
logic diagram (positive logic)
1
1OE
2
1A
4
2OE
5
2A
10
3OE
9
3A
13
4OE
12
4A
3
1Y
6
2Y
8
3Y
11
4Y
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN54AHCT125
SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54AHCT125 SN74AHCT125
MIN MAX
UNIT
MIN MAX
VCC
VIH
VIL
VI
VO
IOH
IOL
Δt/Δv
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
4.5 5.5
2
0.8
0 5.5
0 VCC
−8
8
20
4.5 5.5 V
2V
0.8 V
0 5.5 V
0 VCC V
−8 mA
8 mA
20 ns/V
TA Operating free-air temperature
−55 125 −40
85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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