MUAA2K80M Coprocessor Datasheet

MUAA2K80M Datasheet PDF, Equivalent


Part Number

MUAA2K80M

Description

MUAA Routing Coprocessor

Manufacture

Music Semiconductors

Total Page 24 Pages
PDF Download
Download MUAA2K80M Datasheet PDF


MUAA2K80M
om Data Sheet
MUAAeReto4Uu.tcing CoProcessor (RCP) FamilyAPPLICATION BENEFITS
Sh• High performance MAC Address processor for
tamultiport switches and routers (Up to 48 10/100 or 4
aGigabit Ethernet at wire speed)
.D• Layer 4 flow recognition for Quality of Service up to
16.7 million packets per second
ww• ARP Cache manager/IP address caching at 12.5
w million packets per second
m• Synchronous interfaces and programmable priority
between ports for simplicity of design
o• Learn, age, and auto-age functions with “virtual
.cqueues,” keeping track of aged and learned entries
• Transparent cascade of up to four 2K devices without
t4Uexternal logic, software setup, or performance hit
DISTINCTIVE CHARACTERISTICS
• 2K and 8K x 80-bit partitionable CAM/RAM data
field in address database
• 32-bit synchronous port with separate inputs and
outputs; optional 16-bit configuration
• 32-bit bi-directional processor port; optional 16-bit
configuration
• Pipelined operation
• Operations performed from the synchronous port or
processor port; all flags independently available to
both ports
• 9-bit internal time stamp
• 50 MHz clock
• 388-pin PBGA (8K) and 160-pin PQFP (2K)
packages.
• 3.3 Volt core with 3.3 Volt/5 Volt tolerant IO buffers.
• IEEE 1149.1 (JTAG) compliant
.DataSheePROCD(31:0)
wPROCA(5:0)
/PCS
R/W
PROCREADY
w INT
/RESET
mCLK
Control
16/32 to 80-bit mux
16/32 to 80-bit mux
80-bit latch
80-bit latch
80-bit 2 to 1 mux
Address Data Base
-- b i t 79 -- ------- ------- b i t 0---
Flag and
Chain
Logic
/FF
/MF
CHAIN
CHAINUP
CHAINDN
/CHAINCS
w t4U.co80-bitla tch
80-bit la tch
e80 to 32/16-bit mux
80 to 32/16-bit mux
heTDI
STMS
taTCK
TRST
JTAG
TDO
.DaFigure 1: Block Diagram
wMUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are
wRegistered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
wMUSIC Semiconductors.
March 26, 2003 Rev. 5

MUAA2K80M
MUAA Routing CoProcessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MUSIC MUAA Routing CoProcessor (RCP) family
consists of 80-bit wide content-addressable memories
(CAMs), available in depths of 2K and 8K words. The
CAM/RAM associated data partition is programmable
from 32 bits of CAM and 48 bits of associated data, to 80
bits of CAM and 0 bits of RAM. The MUAA RCP can
perform normal routing functions such as search, insert,
and delete on single entries and can age multiple entries
simultaneously. In addition, there is a learn instruction,
particularly useful in networking applications. For
maximum flexibility all the operations may be performed
either through the processor port or through the
synchronous port. Operations may occur on both ports
simultaneously; the port with the highest priority will gain
access first if both ports require a read or write into the
CAM array simultaneously.
The synchronous interface consists of 32-bit wide input
and output ports, both of which may be configured as 16
bits. The data is multiplexed into and out of the CAM and
RAM associated data field. Where input or output data is
wider than the port, it is loaded or unloaded in multiple
cycles starting with the least significant word. Internally
the device is pipelined; once an operation is started on the
synchronous port the next operation may be loaded and the
results of the previous operation unloaded, thus
maximizing device throughput.
Multiple 2K MUAA RCPs may be chained transparently
to provide deeper memory. No software configuration is
necessary. Each MUAA RCP detects where it is in the
chain from the chaining pins on the previous device. A
register is provided to inform the host of the total available
CAM memory and the number of CAMs chained. All
operations to the chained CAM are totally transparent. No
individual device selection or addressing is required.
The MUSIC MUAA RCP has aging, auto-aging, and
learning functions. All entries have a 9-bit time stamp and
may be marked as static to prevent the aging function from
deleting them. When auto aging is enabled it may be
configured to have higher or lower priority access than the
ports.
Two internal virtual queues of learned and aged entries are
available. As entries are learned or aged out they are
tagged as such and may be read from the device through
either of the ports. This feature enables simple host
management of aged out and learned entries.
IEEE Standard. 1149.1 (JTAG) testability is implemented
providing BYPASS, SAMPLE/PRELOAD, EXTEST,
CLAMP, and HIGH-Z functions.
2 Rev. 5


Features om Data Sheet MUAAeReto4Uu.tcing CoProc essor (RCP) FamilyAPPLICATION BENEFITS Sh• High performance MAC Address proc essor for tamultiport switches and rout ers (Up to 48 10/100 or 4 aGigabit Ethe rnet at wire speed) .D• Layer 4 flow recognition for Quality of Service up t o 16.7 million packets per second ww• ARP Cache manager/IP address caching a t 12.5 w million packets per second m Synchronous interfaces and programmab le priority between ports for simplicit y of design o• Learn, age, and auto-a ge functions with “virtual .cqueues, keeping track of aged and learned en tries • Transparent cascade of up to four 2K devices without t4Uexternal log ic, software setup, or performance hit DISTINCTIVE CHARACTERISTICS • 2K and 8K x 80-bit partitionable CAM/RAM data field in address database • 32-bit s ynchronous port with separate inputs an d outputs; optional 16-bit configuratio n • 32-bit bi-directional processor p ort; optional 16-bit configuration • Pipelined operation • Operations performed from .
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