MU9C4K64 Coprocessor Datasheet

MU9C4K64 Datasheet PDF, Equivalent


Part Number

MU9C4K64

Description

MU9C Routing Coprocessor

Manufacture

Music Semiconductors

Total Page 30 Pages
PDF Download
Download MU9C4K64 Datasheet PDF


MU9C4K64
Data Sheet
MU9C Routing Coprocessor (RCP) Family
APPLICATION BENEFITS
• 28 million IPv4 packets per second supports up to 18
Gb Ethernet or 7 OC-48 ATM ports at wire speed
• Exact match on MAC addresses
• Processes DA and SA within 190 ns, supporting three ports
of 1 Gb or 34 ports of 100 Mb Ethernet at wire
speed
• Mixed mode L3 and L2 single search engine for two ports
at 1 Gb or 29 ports of 100 Mb Ethernet at wire
speed
• Directly addresses external RAM containing
associated data of any width
• Hardware control states directly address memory and
registers; Instruction and Status registers for optional
software control
DISTINCTIVE CHARACTERISTICS
• 4K and 8K x 64-bit words
• 64-bit binary compares
• 35 ns deterministic compare and output time
• 32-bit Data I/O port
• 16-bit Match Address Output port
• Address/Control bus directly controls device operations for
faster operation or higher throughput
• Seven selectable mask registers
• Synchronous operation
• Cascadable for increased depth
• Extensive set of control states for flexibility
• JTAG interface
• 100-pin LQFP package; 3.3 Volt operation
DQ31–0
/VB
/E
/CS1
/CS2
/W
/OE
/AV
AC Bus
/DSC
/RESET
TCLK
TMS
TDI
TDO
/TRST
CONTROL
AND
ADDRESS
DECODER
COMPARAND REGISTER
MASK REGISTERS 1–7
ADDRESS REGISTER
CONFIGURATION REGISTER
STATUS REGISTER
INSTRUCTION REGISTER
DEVICE SELECT REGISTER
4 K x 64 Word
(MU9C4K64)
8 K x 64 Word
(MU9C8K64)
Address Database
AA Bus
PA3–0
PRIORITY
ENCODER
AND
FLAG
LOGIC
/FI
/F F
/M I
/M F
/MM
Figure 1: Block Diagram
MUSIC Semiconductors, the MUSIC logo, and the phrase “MUSIC Semiconductors” are
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of
MUSIC Semiconductors.
June 1 2002 Rev. 6

MU9C4K64
MU9C Binary Routing Coprocessor (RCP) Family
General Description
GENERAL DESCRIPTION
The MU9C RCP family consists of 4K and 8K x 64-bit
Routing Coprocessors (RCPs) with a 32-bit wide data
interface. The device is designed for use in layer 2
switches to provide very high throughput address
translation using tables held in external RAM. The MU9C
RCP has a fully deterministic search time, independent of
the size of the list and the position of the data in the list.
This unique feature guarantees that the wire speed address
recognition does not impact the latency or induce some
jitter on the latency of the global system. Address fields
from the packet header are compared against a list of
entries stored in the array. As a result of the comparison,
the MU9C RCP generates an index that is used to access
an external RAM where port mapping data and other
associated information is stored.
A set of control states provides a powerful and flexible
control interface to the MU9C RCP. This control structure
allows memory read and write, register read and write,
data move, comparison, validity control, addressing
control, and initialization operations.
The MU9C RCP architecture uses direct hardware control
of the device and an independent bus for returning match
results. Software control is also supported for systems
where maximum performance is not needed.
OPERATIONAL OVERVIEW
The MU9C RCP is designed to act as an address translator
for lookup tables in layer 2 switches. Refer to Figure 2 for
a simplified block diagram of a switch. During normal
operation, the controller extracts the address information
from an arriving packet to form the comparand, which is
then compared against the contents of the MU9C RCP.
The MU9C RCP generates an index that is used to access
the data in an external RAM, which holds the destination
port for accessing the network. The controller reads the
data from the RAM and forwards the packet.
The validity of a location in the Address Database is
determined by an extra bit called the Validity bit. This bit is
set and reset either with an index or an associative match.
Therefore, when a new entry is written to the database, its
Validity bit is set valid. The index at which a write takes
place is driven onto the PA:AA bus, so that output port
data can be written simultaneously into the external RAM
at the correct index.
When a database location is deleted, the Validity bit for that
entry is reset, and the index of the location is driven onto
the Active Address bus. This simple mechanism allows
easy maintenance of the tables in both the database and the
external RAM.
The MU9C RCP supports simple daisy chained vertical
cascading that serves to prioritize multiple devices and
provides system-level match and full indication. If the
slight timing overhead associated with the daisy chain is
unacceptable, the MU9C RCP is designed to facilitate
external prioritization across multiple devices.
Packet Stream
Controller
Switch Control
and Packet Data
RCP
Control
Network
Address
MU9C
RAM
Address
Data
RAM
Switch
Fabric
Figure 2: Switch Block Diagram
2 Rev. 6


Features Data Sheet MU9C Routing Coprocessor (RC P) Family APPLICATION BENEFITS • 28 million IPv4 packets per second support s up to 18 Gb Ethernet or 7 OC-48 ATM p orts at wire speed • Exact match on M AC addresses • Processes DA and SA wi thin 190 ns, supporting three ports of 1 Gb or 34 ports of 100 Mb Ethernet at wire speed • Mixed mode L3 and L2 sin gle search engine for two ports at 1 Gb or 29 ports of 100 Mb Ethernet at wire speed • Directly addresses external RAM containing associated data of any w idth • Hardware control states direct ly address memory and registers; Instru ction and Status registers for optional software control DISTINCTIVE CHARACTE RISTICS • 4K and 8K x 64-bit words 64-bit binary compares • 35 ns dete rministic compare and output time • 3 2-bit Data I/O port • 16-bit Match Ad dress Output port • Address/Control b us directly controls device operations for faster operation or higher throughp ut • Seven selectable mask registers • Synchronous operation • Cascadable for increased.
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