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CY7C65620 Controller Datasheet |
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| Part Number | CY7C65620 |
| Description | Low-Power USB 2.0 Hub Controller |
| Manufacture | Cypress Semiconductor |
| Total Page | 30 Pages |
| PDF Download |
CY7C65620
CY7C65630
EZ-USB HX2LP™
Low-Power USB 2.0 Hub Controller Family
EZ-USB HX2LP™ Low-Power USB 2.0 Hub Controller Family
Features
■ USB 2.0 hub controller
■ Automotive and Industrial grade option (–40 °C to 85 °C)
■ Compliant with USB 2.0 specification
■ USB-IF certified: TID# 30000009
■ Windows Hardware Quality Lab (WHQL) Compliant
■ Up to four downstream ports supported
■ Supports bus powered and self powered modes
■ Single transaction translator (TT)
■ Bus power configurations
■ Fit, form, and function compatible with CY7C65640 and
CY7C65640A (TetraHub™)
■ Space saving 56-pin QFN
■ Single power supply requirement
❐ Internal regulator for reduced cost
■ Integrated upstream pull-up resistor
■ Integrated pull-down resistors for all downstream ports
■ Integrated upstream and downstream termination resistors
■ Integrated port status indicator control
Block Diagram – CY7C65630
■ 24 MHz external crystal (integrated phase-locked loop (PLL))
■ In-system EEPROM programming
■ Configurable with external SPI EEPROM:
❐ Vendor ID, Product ID, Device ID (VID/PID/DID)
❐ Number of active ports
❐ Number of removable ports
❐ Maximum power setting for high-speed and full-speed
❐ Hub controller power setting
❐ Power-on timer
❐ Overcurrent detection mode
❐ Enabled and disabled overcurrent timer
❐ Overcurrent pin polarity
❐ Indicator pin polarity
❐ Compound device
❐ Enable full-speed only
❐ Disable port indicators
❐ Ganged power switching
❐ Self and bus powered compatibility
❐ Fully configurable string descriptors for multiple language
support
Functional Description
For a complete list of related documentation, click here.
24 MHz
Crystal
D+ D -
USB 2.0 PHY
PLL
USB Upstream Port
Serial
Interface
Engine
High-Speed
USB Control Logic
SPI Communication
Block
SPI_SCK
SPI_SD
SPI_CS
Hub Repeater
Transaction Translator
TT RAM
Routing Logic
USB Downstream Port 1
USB 2.0 Port Power Port
PHY
Control Status
USB Downstream Port 2
USB 2.0 Port Power Port
PHY
Control Status
USB Downstream Port 3
USB 2.0 Port Power Port
PHY
Control Status
USB Downstream Port 4
USB 2.0 Port Power Port
PHY
Control Status
D+ D- PWR#[1]
LED D+ D- PWR#[2]
LED D+ D- PWR#[3]
LED D+ D- PWR#[4]
LED
OVR#[1]
OVR#[2]
OVR#[3]
OVR#[4]
Errata: For information on silicon errata, see Errata on page 28. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-08037 Rev. AG
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 6, 2019
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Block Diagram – CY7C65620
24 MHz
Crystal
D+ D -
USB 2.0 PHY
PLL
USB Upstream Port
Hub Repeater
CY7C65620
CY7C65630
Serial
Interface
Engine
High-Speed
USB Control Logic
SPI Communication
Block
Transaction Translator (X1)
TT RAM
SPI_SCK
SPI_SD
SPI_CS
Routing Logic
USB Downstream Port 1
USB 2.0 Port Power Port
PHY
Control Status
USB Downstream Port 2
USB 2.0 Port Power Port
PHY
Control Status
D+ D- PWR#[1]
LED
OVR#[1]
D+ D- PWR#[2]
LED
OVR#[2]
Document Number: 38-08037 Rev. AG
Page 2 of 34
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| Features | CY7C65620 CY7C65630 EZ-USB HX2LP™ Low- Power USB 2.0 Hub Controller Family EZ -USB HX2LP™ Low-Power USB 2.0 Hub Con troller Family Features ■ USB 2.0 hub controller ■ Automotive and Industri al grade option (–40 °C to 85 °C) Compliant with USB 2.0 specification ■ USB-IF certified: TID# 30000009 Windows Hardware Quality Lab (WHQL) C ompliant ■ Up to four downstream port s supported ■ Supports bus powered an d self powered modes ■ Single transac tion translator (TT) ■ Bus power conf igurations ■ Fit, form, and function compatible with CY7C65640 and CY7C65640 A (TetraHub™) ■ Space saving 56-pin QFN ■ Single power supply requiremen t ❐ Internal regulator for reduced co st ■ Integrated upstream pull-up resi stor ■ Integrated pull-down resistors for all downstream ports ■ Integrate d upstream and downstream termination r esistors ■ Integrated port status ind icator control Block Diagram – CY7C65 630 ■ 24 MHz external crystal (integrated phase-locked loop (PLL)) ■ In-system EEPROM programming ■ Configur. |
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