XO2-640U1 MachXO2 Datasheet

XO2-640U1 Datasheet PDF, Equivalent


Part Number

XO2-640U1

Description

MachXO2

Manufacture

Lattice

Total Page 30 Pages
Datasheet
Download XO2-640U1 Datasheet


XO2-640U1
MachXO2™ Family Data Sheet
DS1035 Version 3.3, March 2017

XO2-640U1
MachXO2 Family Data Sheet
Introduction
May 2016
Data Sheet DS1035
Features
Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and
18 to 334 I/Os
Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 22 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
Embedded and Distributed Memory
• Up to 240 kbits sysMEM™ Embedded Block
RAM
• Up to 54 kbits Distributed RAM
• Dedicated FIFO control logic
On-Chip User Flash Memory
• Up to 256 kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and
JTAG interfaces
• Can be used as soft processor PROM or as
Flash memory
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
DQS support
High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5 V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O
interfaces (top and bottom sides only)
• Up to two analog PLLs per device with
fractional-n frequency synthesis
– Wide input frequency range (7 MHz to
400 MHz)
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2C
• Supports background programming of non-vola-
tile memory
• Optional dual boot with external SPI memory
TransFR™ Reconfiguration
• In-field logic update while system operates
Enhanced System Level Support
• On-chip hardened functions: SPI, I2C, timer/
counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Broad Range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
fpBGA, QFN package options
• Small footprint package options
– As small as 2.5 mm x 2.5 mm
• Density migration supported
• Advanced halogen-free packaging
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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1-1 DS1035 Introduction_02.2


Features MachXO2™ Family Data Sheet DS1035 Vers ion 3.3, March 2017 MachXO2 Family Dat a Sheet Introduction May 2016 Data Sh eet DS1035 Features  Flexible Logic Architecture • Six devices with 256 to 6864 LUT4s and  18 to 334 I/Os Ultra Low Power Devices • Advanced 65 nm low power process • As low as 2 2 µW standby power • Programmable lo w swing differential I/Os • Stand-by mode and other power saving options  Embedded and Distributed Memory • Up to 240 kbits sysMEM™ Embedded Block RAM • Up to 54 kbits Distributed RAM • Dedicated FIFO control logic  On -Chip User Flash Memory • Up to 256 k bits of User Flash Memory • 100,000 w rite cycles • Accessible through WISH BONE, SPI, I2C and JTAG interfaces • Can be used as soft processor PROM or a s Flash memory  Pre-Engineered Sourc e Synchronous I/O • DDR registers in I/O cells • Dedicated gearing logic 7:1 Gearing for Display I/Os • Gen eric DDR, DDRX2, DDRX4 • Dedicated DDR/DDR2/LPDDR memory with DQS support  High Performance, Flexible I/O Buffe.
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