CSD97374Q4M Stage Datasheet

CSD97374Q4M Datasheet PDF, Equivalent


Part Number

CSD97374Q4M

Description

Synchronous Buck NexFET Power Stage

Manufacture

etcTI

Total Page 22 Pages
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CSD97374Q4M
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CSD97374Q4M
SLPS382D – JANUARY 2013 – REVISED AUGUST 2016
CSD97374Q4M Synchronous Buck NexFET™ Power Stage
Not Recommended for New Designs
1 Features
1 Over 92% System Efficiency at 15 A
• Max Rated Continuous Current 25 A, Peak 60 A
• High-Frequency Operation (up to 2 MHz)
• High-Density SON 3.5-mm x 4.5-mm Footprint
• Ultra-Low Inductance Package
• System Optimized PCB Footprint
• Ultra-Low Quiescent (ULQ) Current Mode
• 3.3-V and 5-V PWM Signal Compatible
• Diode Emulation Mode with FCCM
• Input Voltages up to 24 V
• Tri-State PWM Input
• Integrated Bootstrap Diode
• Shoot-Through Protection
• RoHS Compliant – Lead-Free Terminal Plating
• Halogen Free
2 Applications
• Ultrabook/Notebook DC/DC Converters
• Multiphase Vcore and DDR Solutions
• Point-of-Load Synchronous Buck in Networking,
Telecom, and Computing Systems
Application Diagram
3 Description
The CSD97374Q4M NexFET™ power stage is a
highly optimized design for use in a high-power, high-
density synchronous buck converter. This product
integrates the driver IC and NexFET technology to
complete the power stage switching function. The
driver IC has a built-in selectable diode emulation
function that enables DCM operation to improve light
load efficiency. In addition, the driver IC supports
ULQ mode that enables Connected Standby for
Windows™ 8. With the PWM input in tri-state,
quiescent current is reduced to 130 µA, with
immediate response. When SKIP# is held at tri-state,
the current is reduced to 8 µA (typically 20 µs is
required to resume switching). This combination
produces a high-current, high-efficiency, and high-
speed switching device in a small 3.5-mm × 4.5-mm
outline package. In addition, the PCB footprint has
been optimized to help reduce design time and
simplify the completion of the overall system design.
Device Information(1)
DEVICE
QTY MEDIA
PACKAGE
CSD97374Q4M 2500 13-Inch Reel
SON
3.50-mm × 4.50-mm
Plastic Package
SHIP
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
.
.
100
Typical Power Stage Efficiency and Power Loss
12
90 10
80
VDD = 5 V
70
VIN = 12 V
VOUT = 1.8 V
LOUT = 0.29 PH
60 fSW = 500 kHz
TA = 25qC
50
8
6
4
2
40 0
0 5 10 15 20 25
Output Current (A)
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

CSD97374Q4M
Not Recommended for New Designs
CSD97374Q4M
SLPS382D – JANUARY 2013 – REVISED AUGUST 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information .................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics .............................................. 6
7 Detailed Description .............................................. 8
7.1 Functional Block Diagram ......................................... 8
7.2 Powering CSD97374Q4M and Gate Drivers ............ 8
7.3 Undervoltage Lockout Protection (UVLO)................. 8
7.4 PWM Pin ................................................................... 9
7.5 SKIP# Pin.................................................................. 9
7.6 Integrated Boost-Switch .......................................... 10
8 Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Power Loss Curves ................................................ 11
8.3 Safe Operating Curves (SOA) ................................ 11
8.4 Normalized Curves.................................................. 11
8.5 Calculating Power Loss and SOA .......................... 12
9 Layout ................................................................... 14
9.1 Layout Guidelines ................................................... 14
9.2 Layout Example ...................................................... 15
10 Device and Documentation Support ................. 16
10.1 Receiving Notification of Documentation Updates 16
10.2 Community Resources.......................................... 16
10.3 Trademarks ........................................................... 16
10.4 Electrostatic Discharge Caution ............................ 16
10.5 Glossary ................................................................ 16
11 Mechanical, Packaging, and Orderable
Information ........................................................... 16
11.1 Recommended PCB Land Pattern........................ 18
11.2 Recommended Stencil Opening ........................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July 2013) to Revision D
Page
• Added description of internal connection to pin 7 in the Pin Functions table......................................................................... 3
• Added ESD Ratings table....................................................................................................................................................... 4
• Added a NOTE to the Application and Implementation section ........................................................................................... 11
• Added Layout section ........................................................................................................................................................... 14
• Added the Device and Documentation Support section....................................................................................................... 16
• Changed Mechanical Data section to Mechanical, Packaging, and Orderable Information section.................................... 16
Changes from Revision B (May 2013) to Revision C
Page
• Added dimension row b2 to the MECHANICAL DATA table................................................................................................ 17
Changes from Revision A (March 2013) to Revision B
Page
• Changed the Mechanical Drawing image............................................................................................................................. 16
• Changed the Recommended PCB Land Pattern image....................................................................................................... 18
• Changed the Recommended Stencil Opening image .......................................................................................................... 18
Changes from Original (January 2013) to Revision A
Page
• Changed the ROC table, From: VSW to PGND, VIN to VSW (<20ns) MIN = -5 To: VSW to PGND, VIN to VSW (<10ns) MIN
= -7 ......................................................................................................................................................................................... 4
• Changed the ROC table, From: BOOT to PGND (<20ns) MIN = -3 To: BOOT to PGND (<10ns) MIN = -2 .............................. 4
• Changed Logic Level High, VIH From: MAX = 2.6 To: MIN = 2.65......................................................................................... 5
• Changed Logic Level Low, VIL From: MIN = 0.6 To: MAX = 0.6 ............................................................................................ 5
• Changed Tri-State Voltage, VTS From: MIN = 1.2 To: MIN = 1.3 ........................................................................................... 5
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CSD97374Q4M SLPS382D – JAN UARY 2013 – REVISED AUGUST 2016 CSD97 374Q4M Synchronous Buck NexFET™ Power Stage Not Recommended for New Designs 1 Features •1 Over 92% System Effici ency at 15 A • Max Rated Continuous C urrent 25 A, Peak 60 A • High-Frequen cy Operation (up to 2 MHz) • High-Den sity SON 3.5-mm x 4.5-mm Footprint • Ultra-Low Inductance Package • System Optimized PCB Footprint • Ultra-Low Quiescent (ULQ) Current Mode • 3.3-V and 5-V PWM Signal Compatible • Diode Emulation Mode with FCCM • Input Vol tages up to 24 V • Tri-State PWM Inpu t • Integrated Bootstrap Diode • Sh oot-Through Protection • RoHS Complia nt – Lead-Free Terminal Plating • H alogen Free 2 Applications • Ultraboo k/Notebook DC/DC Converters • Multiph ase Vcore and DDR Solutions • Point-o f-Load Synchronous Buck in Networking, Telecom, and Computing Systems Application Diagram 3 Description The CSD97374Q4M NexFET™ power stage is a .
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