Alterable EEPROM. X28C010 Datasheet

X28C010 EEPROM. Datasheet pdf. Equivalent

X28C010 Datasheet
Recommendation X28C010 Datasheet
Part X28C010
Description Byte Alterable EEPROM
Feature X28C010; X28C010, X28HT010 5V, Byte Alterable EEPROM NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEM.
Manufacture Renesas
Datasheet
Download X28C010 Datasheet




Renesas X28C010
X28C010, X28HT010
5V, Byte Alterable EEPROM
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN8105
Rev 1.00
February 12, 2007
The Intersil X28C010/X28HT010 is a 128K x 8 EEPROM,
fabricated with Intersil's proprietary, high performance,
floating gate CMOS technology. Like all Intersil
programmable non-volatile memories, the
X28C010/X28HT010 is a 5V only device. The
X28C010/X28HT010 features the JEDEC approved pin out
for byte-wide memories, compatible with industry standard
EEPROMs.
The X28C010/X28HT010 supports a 256-byte page write
operation, effectively providing a 19µs/byte write cycle and
enabling the entire memory to be typically written in less
than 2.5 seconds. The X28C010/X28HT010 also features
DATA Polling and Toggle Bit Polling, system software
support schemes used to indicate the early completion of a
write cycle. In addition, the X28C010/X28HT010 supports
Software Data Protection option.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Data retention is specified to
be greater than 100 years.
Features
• Access time: 120ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VPP control
circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low power CMOS
- Active: 50mA
- Standby: 500µA
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Writecell
- Endurance: 100,000 write cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• X28HT010 is fuly functional @ +175°C
Pinouts
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
CERDIP
Flat Pack
SOIC (R)
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 X28C010 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PGA
15I/O0 17I/O2 19I/O3 21I/O5 22I/O6
A1 A0 I/O1 VSS I/O4 I/O7 CE
13 14 16 18 20 23 24
12A2 11A3
25A10
OE
26
A4
10
A5
9
X28C010
(Bottom View)
A11 A 9
27 28
8A6 7A7
29A8
A
30
13
A12 A15 NC VCC NC NC A 14
6 5 2 36 34 32 31
4A16
NC
3
NC WE NC
1 35 33
EXTENDED LCC
4 3 2 32 31 30
A7 5
A6 6
A5 7
1
29 A14
28 A13
27 A8
A4
A3
A2
8
9
10
X28C010
(Top View)
26
25
24
A9
A11
OE
A1 11
23 A10
A0 12
22 CE
I/O 0 13
21 I/O7
14 15 16 17 18 19 20
FN8105 Rev 1.00
February 12, 2007
Page 1 of 20



Renesas X28C010
X28C010, X28HT010
Ordering Information
PART NUMBER
X28C010D-12
X28C010D-15
X28C010DI
X28C010DI-12
X28C010DI-15
X28C010DM
X28C010DM-12
X28C010DM-15
X28C010DMB-12
X28C010DMB-15
X28C010DMB-20
X28C010FI-12
X28C010FI-15
X28C010FI-20
X28C010FM
X28C010FM-12
X28C010FMB-12
X28C010FMB-15
X28C010K-25
X28C010KM-12
X28C010KM-25
X28C010KMB-12
X28C010KMB-15
X28C010NM-12
X28C010NM-15
X28C010NMB-12
X28C010NMB-15
X28C010RI-12
X28C010RI-20
X28C010RI-20T1
X28C010RM-15
X28C010RMB-25
X28HT010W
PART MARKING
X28C010D-12
X28C010D-15
X28C010DI
X28C010DI-12
X28C010DI-15
X28C010DM
X28C010DM-12
X28C010DM-15
C X28C010DMB-12
C X28C010DMB-15
C X28C010DMB-20
X28C010FI-12
X28C010FI-15
X28C010FI-20
X28C010FM
X28C010FM-12
C X28C010FMB-12
C X28C010FMB-15
X28C010K-25
X28C010KM-12
X28C010KM-25
C X28C010KMB-12
C X28C010KMB-15
X28C010NM-12
X28C010NM-15
C X28C010NMB-12
C X28C010NMB-15
X28C010RI-12
X28C010RI-20
X28C010RI-20
X28C010RM-15
C X28C010RMB-25
ACCESS
TIME
120ns
150ns
-
120ns
150ns
-
120ns
150ns
120ns
150ns
200ns
120ns
150ns
200ns
-
120ns
120ns
150ns
250ns
120ns
250ns
120ns
150ns
120ns
150ns
120ns
150ns
120ns
200ns
200ns
150ns
250ns
200ns
TEMP RANGE
(°C)
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-55 to +125
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
MIL-STD-883
-40 to +85
-40 to +85
-40 to +85
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
0 to +70
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
-55 to +125
-55 to +125
MIL-STD-883
MIL-STD-883
-40 to +85
-40 to +85
-40 to +85
-55 to +125
MIL-STD-883
-40 to +175
PACKAGE
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Cerdip
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
32-Ld Flat Pack
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
36-Ld Pin Grid Array
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Extended LCC
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
32-Ld Ceramic SOIC (Gull Wing)
Wafer
PKG. DWG #
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
F32.6
G36.760x760A
G36.760x760A
G36.760x760A
G36.760x760A
G36.760x760A
FN8105 Rev 1.00
February 12, 2007
Page 2 of 20



Renesas X28C010
X28C010, X28HT010
Block Diagram
A8-A16
X Buffers
Latches and
Decoder
1Mbit
EEPROM
Array
A0-A7
Y Buffers
Latches and
Decoder
I/O Buffers
and Latches
CE Control
OE Logic and
WE Timing
I/O0-I/O7
Data Inputs/Outputs
VCC
VSS
Pin Descriptions
Addresses (A0-A16)
The Address inputs select an 8-bit memory location during a
read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers, and
is used to initiate read operations.
Data In/Data Out (I/O0-I/O7)
Data is written to or read from the X28C010/X28HT010
through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C010/X28HT010.
Back Bias Voltage (VBB) (X28HT010 only)
It is required to provide -3V on pin 1. This negative voltage
improves higher temperature functionality.
Pin Names
SYMBOL
A0-A16
I/O0-I/O7
WE
CE
OE
VCC
VSS
NC
VBB*
*VBB applies to X28HT010 only.
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
-3V
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in a
high impedance state when either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE are LOW
and OE is HIGH. The X28C010/X28HT010 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs last.
Similarly, the data is latched internally by the rising edge of
either CE or WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion,
typically within 5ms.
FN8105 Rev 1.00
February 12, 2007
Page 3 of 20





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