PCM5122 DAC Datasheet

PCM5122 Datasheet, PDF, Equivalent


Part Number

PCM5122

Description

112-dB and 106-dB Audio Stereo DAC

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download PCM5122 Datasheet


PCM5122
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PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
PCM512x 2-VRMS DirectPath™, 112-dB and 106-dB Audio Stereo DACs
With 32-Bit, 384-kHz PCM Interface
1 Features
1 Register-Selectable Audio-Processing Functions
up to 48-kHz fS
– Dynamic Range Control (DRC)
– Equalization (EQ)
– Filtering
• DAC Functionality to 384-kHz fS
• Market-Leading Low Out-of-Band Noise
• Selectable Digital-Filter Latency and Performance
• No DC-Blocking Capacitors Required
• Integrated Negative Charge Pump
• Intelligent Muting System; Soft Up or Down Ramp
and Analog Mute for 120-dB Mute SNR
• Integrated High-Performance Audio PLL With
BCK Reference to Generate SCK Internally
• Accepts 16-, 20-, 24-, and 32-Bit Audio Data
• PCM Data Formats: I2S, Left-Justified, Right-
Justified, TDM / DSP
• SPI or I2C Control
• Software or Hardware Configuration
• Automatic Power-Save Mode When LRCK and
BCK are Deactivated
• 1.8-V or 3.3-V Failsafe LVCMOS Digital Inputs
• Single Supply Operation:
– 3.3-V Analog, 1.8-V or 3.3-V Digital
• Integrated Power-On Reset
• Small28-Pin Package
2 Applications
3 Description
The PCM512x devices are a family of monolithic
CMOS-integrated circuits that include a stereo digital-
to-analog converter and additional support circuitry in
a small TSSOP package. The PCM512x uses the
latest generation of TI’s advanced segment-DAC
architecture to achieve excellent dynamic
performance and improved tolerance to clock jitter.
Members of the PCM512x family integrate preset
audio processing functions with programmable
coefficients, allowing developers to change the
characteristics of the interpolation filter, speaker EQ,
dynamic range controls, and average volume control
in their products.
The PCM512x provides 2.1-VRMS ground-centered
outputs, allowing designers to eliminate DC-blocking
capacitors on the output, as well as external muting
circuits traditionally associated with single supply line
drivers.
The integrated line driver surpasses all other charge-
pump-based line drivers by supporting loads down to
1 kΩ. By supporting loads down to 1 kΩ, the
PCM512x can essentially drive up to 10 products in
parallel (LCD TV, DVDR, AV receivers, and so forth).
The integrated PLL on the device removes the
requirement for a system clock (commonly known as
master clock), allowing a 3-wire I2S connection, along
with reducing system EMI.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
PCM5121
PCM5122
TSSOP (28)
9.7 mm × 4.4 mm
• A/V Receivers
• DVD, BD Players
• HDTV Receivers
• Applications Requiring 2-VRMS Audio Output
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Simplified System Diagram
2ch Single Ended
PCM1863/5
IN
AUX
2ch Single Ended
I2S
BCK
LRCK
Audio
Processing
Blocks,
Filters
DOUT
Current Segment DAC
PCM512x
Analog
Sensor
- Light Intensity
- Ultrasonic
- Battery Level
BT Module
MSP430
WiLAN chip
TPA3130
TPA6120A2
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

PCM5122
PCM5121, PCM5122
SLAS763C – AUGUST 2012 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison ............................................... 4
6 Pin Configuration and Functions ......................... 5
6.1 Pin Functions ............................................................ 5
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings ............................................................ 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information .................................................. 7
7.5 Electrical Characteristics........................................... 8
7.6 Timing Requirements: SCK Input ........................... 11
7.7 Timing Requirements: XSMT .................................. 11
7.8 Switching Characteristics ........................................ 11
7.9 Typical Characteristics ............................................ 12
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 51
8.5 Programming........................................................... 57
9 Application and Implementation ........................ 58
9.1 Application Information............................................ 58
9.2 Typical Application .................................................. 58
10 Power Supply Recommendations ..................... 60
10.1 Power Supply Distribution and Requirements ...... 60
10.2 Recommended Powerdown Sequence................. 60
10.3 External Power Sense Undervoltage Protection
Mode ........................................................................ 62
10.4 Power-On Reset Function..................................... 64
10.5 PCM512x Power Modes ....................................... 65
11 Layout................................................................... 66
11.1 Layout Guidelines ................................................. 66
11.2 Layout Example .................................................... 66
12 Register Maps...................................................... 67
12.1 PCM512x Register Map ........................................ 67
13 Device and Documentation Support ............... 113
13.1 Development Support ......................................... 113
13.2 Documentation Support ...................................... 113
13.3 Related Links ...................................................... 113
13.4 Receiving Notification of Documentation
Updates.................................................................. 113
13.5 Community Resources........................................ 113
13.6 Trademarks ......................................................... 113
13.7 Electrostatic Discharge Caution .......................... 113
13.8 Glossary .............................................................. 113
14 Mechanical, Packaging, and Orderable
Information ......................................................... 114
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2016) to Revision C
Page
• Added bullet item with additional description for 3-wire mode operation to Design Requirements section ........................ 58
Changes from Revision A (September 2012) to Revision B
Page
• Changed Accepts 16-, 24-, And 32-Bit Audio Data to Accepts 16-, 20-, 24-, And 32-Bit Audio Data ................................... 1
• Deleted Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts, .. With Popless Operation .......................... 1
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes section, Application and Implementation section, Power Supply Recommendations section, Layout section,
Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................... 1
• Clarified Pin Functions table................................................................................................................................................... 5
• Deleted redundant PLL specification in Recommended Operating Conditions .................................................................... 7
• Deleted Intelligent clock error... and ...for pop-free performance in the Overview section. ................................................. 14
• Added note on instruction cycle requirements. .................................................................................................................... 20
• Added note on instruction cycles in Fixed Audio Processing Flow (Program 5).................................................................. 34
• Changed Ouptut to Output ................................................................................................................................................... 42
• Deleted VREF mode provides 2.1Vrms full-scale output at both AVDD levels...................................................................... 42
• Clarified clock generation explanation in Reset and System Clock Functions..................................................................... 45
• Clarified external SCK discussion in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)........... 47
• Deleted The PCM512x disables the internal PLL when an external SCK is supplied. ........................................................ 47
2 Submit Documentation Feedback
Copyright © 2012–2018, Texas Instruments Incorporated
Product Folder Links: PCM5121 PCM5122


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity PCM5121, PCM5122 SLAS763C – A UGUST 2012 – REVISED OCTOBER 2018 PCM 512x 2-VRMS DirectPath™, 112-dB and 1 06-dB Audio Stereo DACs With 32-Bit, 38 4-kHz PCM Interface 1 Features •1 Re gister-Selectable Audio-Processing Func tions up to 48-kHz fS – Dynamic Range Control (DRC) – Equalization (EQ) Filtering • DAC Functionality to 38 4-kHz fS • Market-Leading Low Out-of- Band Noise • Selectable Digital-Filte r Latency and Performance • No DC-Blo cking Capacitors Required • Integrate d Negative Charge Pump • Intelligent Muting System; Soft Up or Down Ramp and Analog Mute for 120-dB Mute SNR • In tegrated High-Performance Audio PLL Wit h BCK Reference to Generate SCK Interna lly • Accepts 16-, 20-, 24-, and 32-B it Audio Data • PCM Data Formats: I2S , Left-Justified, Right- Justified, TDM / DSP • SPI or I2C Control • Softw are or Hardware Configuration • Automatic Power-Save Mode When LRCK and BCK are Deactivated • 1.8-V.
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