Backup Unit. bq2502 Datasheet
® Power monitoring, backup supply,
and switching for 3V battery-
® Write-protect control
® Input decoder for control of up to
2 banks of SRAM
® 3-volt backup power output
® Internal 130mAh lithium-coin
® Reset output for system power-on
® Less than 10ns chip-enable
® 5% or 10% supply operation
Integrated Backup Unit
The CMOS bq2502 Integrated Backup
Unit provides all the necessary func-
tions for converting one or two
banks of standard CMOS SRAM
into nonvolatile read/write memory.
A precision comparator monitors the 5V
VCC input for an out-of-tolerance condi-
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect both
banks of SRAM.
Power for the external SRAMs is
switched from the VCC supply to the
internal battery-backup supply as
VCC decays. On a subsequent
power-up, the VOUT supply is auto-
matically switched from the internal
lithium supply to the VCC supply.
The external SRAMs are write-pro-
tected until a power-valid condition
exists. The reset output provides
power-fail and power-on resets for the
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
The internal lithium cell is initially
electrically isolated, protecting the
battery from accidental discharge.
Connection to the battery is made
only after the first application of
12-Pin 600-mil DIP Module
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
A Bank select input
NC No connect
VCC 5-volt supply input
Two banks of CMOS static RAM can be battery-backed
using the VOUT and conditioned chip-enable output pins
from the bq2502. As the voltage input VCC slews down
during a power failure, the two conditioned chip-enable
outputs, CECON1 and CECON2, are forced inactive
independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM
as VCC falls to an out-of-tolerance threshold VPFD. VPFD is
selected by the threshold-select input pin, THS. If THS is
tied to VSS, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
If THS is tied to VOUT, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to VSS or VOUT for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time tWPT (150µs maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.
As the supply continues to fall past VPFD, an internal
switching device forces VOUT to the internal backup en-
ergy source. CECON1 and CECON2 are held high by the
VOUT energy source.
During power-up, VOUT is switched back to the 5V sup-
ply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CECON1 and CECON2 are held
inactive for time tCER (120ms maximum) after the
power supply has reached VPFD, independent of the CE
input, to allow for processor stabilization.
The reset output (RST) goes active within tR (150µs
maximum) after VPFD, and remains active for a mini-
mum of 40ms (120ms maximum) after power returns
valid. The RST output can be used as the power-on re-
set for a microprocessor. Access to the external RAM
may begin when RST returns inactive.
During power-valid operation, the CE input is passed
through to one of the two CECON outputs with a propa-
gation delay of less than 10ns. The CE input is output on
one of the two CECON output pins depending on the
level of bank select input A, as shown in the Truth Ta-
Bank select input A is usually tied to a high-order address
pin so that a large nonvolatile memory can be designed
using lower-density memory devices. Nonvolatility and de-
coding are achieved by hardware hookup, as shown in Fig-
The internal lithium cell is capable of supplying 3V on
VOUT for an extended period. The cumulative length of
time that the external SRAMs retain data in the ab-
sence of power is a function of the data-retention cur-
rent of the SRAMs used. The initial capacity of the in-
ternal lithium cell is 130mAh. Typically, if the data- re-
tention currents for two external SRAMs are 1µA per
SRAM at room temperature, nonvolatility is calculated
to be for more than 7 years. If only one external SRAM
is used, the data-retention time increases to more than
The bq2502 battery life is a function of the time spent in
battery-backed mode and the data-retention current of
the external SRAM. For example, office equipment is
generally powered on for 8 hours and powered off for 16
hours. Under these conditions, a single bq2502 provides
SRAMs drawing 2µA total data-retention current with
more than 10 years of nonvolatility.
Figure 1. Hardware Hookup (5% Supply Operation)
As shipped from Benchmarq, the internal lithium cell is
electrically isolated from VOUT, CECON1, and CECON2.
Self-discharge in this condition is less than 0.5% per
year at 20°C.
Note: Following the first application of VCC, this isola-
tion is broken, and the backup cell provides power to
VOUT, CECON1, and CECON2 for the external SRAM.
Take care to avoid inadvertent discharge through
VOUT, CECON1, and CECON2 after battery isolation
has been broken.
This isolation can be reestablished by applying a valid
isolation signal to the bq2502. See Figure 2. This signal
requires CE low as VCC crosses both VPFD and VSO dur-
ing a power--down. Between these two points in time,
CE must be brought to (0.48 to 0.52) * VCC and held for
at least 700ns. The isolation signal is invalid if CE ex-
ceeds 0.54*VCC at any point between VCC crossing
VPFD and VSO.
The battery is connected to VOUT immediately on subse-
quent application and removal of VCC.
Figure 2. Battery Isolation Signal