SN54HC7032 GATES Datasheet

SN54HC7032 Datasheet, PDF, Equivalent


Part Number

SN54HC7032

Description

QUADRUPLE POSITIVE-OR GATES

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN54HC7032 Datasheet


SN54HC7032
D Wide Operating Voltage Range of 2 V to 6 V
D Operation From Very Slow Input
Transitions
D Same Pinouts as ’HC32
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
D Typical tpd = 14 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
D Temperature-Compensated Threshold
Levels
D High Noise Immunity
SN54HC7032, SN74HC7032
QUADRUPLE POSITIVEĆOR GATES
WITH SCHMITTĆTRIGGER INPUTS
SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
SN54HC7032 . . . J OR W PACKAGE
SN74HC7032 . . . D, N, OR NS PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
SN54HC7032 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
In these devices, each circuit functions as a
quadruple OR gate. They perform the Boolean
function Y + A B or Y + A ) B in positive
logic. However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
1Y
3 2 1 20 19
4 18
4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC7032N
SN74HC7032N
Tube of 50
SN74HC7032D
−40°C to 85°C SOIC − D
Reel of 2500
Reel of 250
SN74HC7032DR
SN74HC7032DT
HC7032
SOP − NS
Reel of 2000 SN74HC7032NSR HC7032
CDIP − J
Tube of 25
SNJ54HC7032J
SNJ54HC7032J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC7032W
SNJ54HC7032W
LCCC − FK
Tube of 55
SNJ54HC7032FK SNJ54HC7032FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HX
H
XH
H
LL
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
1

SN54HC7032
SN54HC7032, SN74HC7032
QUADRUPLE POSITIVEĆOR GATES
WITH SCHMITTĆTRIGGER INPUTS
SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7032
MIN NOM MAX
SN74HC7032
UNIT
MIN NOM MAX
VCC Supply voltage
2 5 6 2 5 6V
VI Input voltage
0
VCC
0
VCC V
VO Output voltage
0
VCC
0
VCC V
TA Operating free-air temperature
−55 125 −40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Wide Operating Voltage Range of 2 V to 6 V D Operation From Very Slow Input T ransitions D Same Pinouts as ’HC32 D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC D Typical tpd = 14 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 A Max D Temperature-Compensated Thresh old Levels D High Noise Immunity SN54H C7032, SN74HC7032 QUADRUPLE POSITIVEĆO R GATES WITH SCHMITTĆTRIGGER INPUTS SC LS036E − MARCH 1984 − REVISED NOVEM BER 2004 SN54HC7032 . . . J OR W PACKAG E SN74HC7032 . . . D, N, OR NS PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y SN54HC7032 . . . FK PACKA GE (TOP VIEW) 3A 4B VCC NC NC GND 1 A 2Y 1B description/ordering informat ion In these devices, each circuit func tions as a quadruple OR gate. They perf orm the Boolean function Y + A • B or Y + A ) B in positive logic. However, because of the Schmitt action, the inpu ts have different input threshold levels for positive- and negative-going si.
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