DS125BR820 Repeater Datasheet

DS125BR820 Datasheet, PDF, Equivalent


Part Number

DS125BR820

Description

Low-Power 12.5 Gbps 8-Channel Linear Repeater

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download DS125BR820 Datasheet


DS125BR820
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
DS125BR820 Low-Power 12.5 Gbps 8-Channel Linear Repeater
1 Features
1 Low 70 mW/Channel (Typ) Power Consumption,
with Option to Power Down Unused Channels
• Seamless Link Training Support
• Enables Host ASIC to Meet Front-Port Eye Mask
Requirements over Longer Reach
• Advanced Configurable Signal Conditioning I/O
– Receive CTLE up to 10 dB at 6 GHz
– Linear Output Driver
– Variable Output Voltage Range up to 1200
mVp-p
• Programmable via Pin Selection, EEPROM, or
SMBus Interface
• Single Supply Voltage: 2.5 V or 3.3 V
40°C to 85°C Operating Temperature Range
• Flow-Thru Layout in 10 mm × 5.5 mm 54-Pin
Leadless WQFN Package
2 Applications
• Front-Port 40G-CR4/SR4/LR4 Link Extension
• Backplane 40G-KR4 Link Extension
• SAS/SATA/PCIe Link Extension
• Other Proprietary High Speed Interfaces up to
12.5 Gbps
Simplified Functional Block Diagram
INB_0+
. INB. _0-
..
..
INB_3+
INB_3-
OUTB_0+
.
OUTB_.0-
.
. ..
. ..
OUTB_3+
OUTB_3-
INA_0+
. INA. _0-
..
..
INA_3+
INA_3-
OUTA_0+
.
OUTA_.0-
.
. ..
. ..
OUTA_3+
OUTA_3-
Address
straps
(pull-up or
pull-down)
SMBus
Slave Mode(1)
AD0
AD1
AD2
AD3
READ_EN
2.5V
2.5 V
Mode(3)
10F 1F
0.1F
(5x)
VIN
VDD_SEL
VDD
ENSMB
SDA(2)
SCL(2)
ALL_DONE
GND
VDD
SMBus
Slave Mode(1)
To system
SMBus
3 Description
The DS125BR820 is an extremely low-power high-
performance repeater/redriver designed to support
eight channels carrying high speed interface up to
12.5 Gbps, such as 40G-CR4, 40G-KR4, SAS/SATA,
and PCIe. The receiver's continuous time linear
equalizer (CTLE) provides high frequency boost that
is programmable from 3 to 10 dB at 6 GHz (12 Gbps)
followed by a linear output driver. The CTLE receiver
is capable of opening an input eye that is completely
closed due to inter symbol interference (ISI) induced
by interconnect medium such as board traces or twin
axial-copper cables. The programmable equalization
maximizes the flexibility of physical placement within
the interconnect channel and improves overall
channel performance.
When operating in 40G-CR4/KR4, SAS/SATA, and
PCIe applications, the DS125BR820 preserves
transmit signal characteristics, thereby allowing the
host controller and the end point to negotiate transmit
equalizer coefficients. This transparency in the link
training protocol facilitates system level
interoperability and minimizes latency.
The programmable settings can be applied easily via
pin control, software (SMBus or I2C), or direct loading
from an external EEPROM. In EEPROM mode, the
configuration information is automatically loaded on
power up, thereby eliminating the need for an
external microprocessor or software driver.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS125BR820
WQFN (54)
10 mm × 5.5 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram
Line Card
ASIC
FPGA
2x40G
DS125BR820
DS125BR820
2x40G
Stacked QSFP+
40GbE Copper CR4 or
40GbE SR4/LR4 Optical
8x10G
DS125BR820
DS125BR820
8x10G
Stacked QSFP+
1xQSFP+ to 4xSFP+
Breakout
(1) Schematic requires different connections for SMBus Master Mode and Pin Mode
(2) SMBus signals need to be pulled up elsewhere in the system.
(3) Schematic requires different connections for 3.3 V mode
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS125BR820
DS125BR820
SNLS491B – JULY 2014 – REVISED FEBRUARY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information ................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Electrical Characteristics — Serial Bus Interface DC
Specifications ........................................................... 10
6.7 Serial Bus Interface Timing Specifications ........ 10
6.8 Typical Characteristics ............................................ 12
7 Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 14
7.5 Signal Conditioning Settings ................................... 15
7.6 Programming........................................................... 17
7.7 Register Maps ......................................................... 25
8 Applications and Implementation ...................... 40
8.1 Application Information............................................ 40
8.2 Typical Applications ................................................ 41
9 Power Supply Recommendations...................... 52
10 Layout................................................................... 53
10.1 Layout Guidelines ................................................. 53
10.2 Layout Example .................................................... 53
11 Device and Documentation Support ................. 54
11.1 Trademarks ........................................................... 54
11.2 Electrostatic Discharge Caution ............................ 54
11.3 Glossary ................................................................ 54
12 Mechanical, Packaging, and Orderable
Information ........................................................... 54
4 Revision History
Changes from Revision A (September 2014) to Revision B
Page
• Added data type for all differential high speed I/O ................................................................................................................ 4
• Changed pin assignment numbers for OUTB_2+/- and OUTB_3+/- to correct typo.............................................................. 4
• Changed ENSMB pin type to 4-level LVCMOS per input pin behavior.................................................................................. 4
• Changed Handling Ratings table to ESD Ratings table ........................................................................................................ 7
• Changed register map rows to combine multiple consecutive registers with a value of all zeros and no EEPROM-
relevant bits .......................................................................................................................................................................... 28
Changes from Original (July 2014) to Revision A
Page
• Added release of the full document ....................................................................................................................................... 1
2 Submit Documentation Feedback
Copyright © 2014–2015, Texas Instruments Incorporated


Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DS125BR820 SNLS491B – JULY 2014 – REVISED FEBRUARY 2015 DS125BR 820 Low-Power 12.5 Gbps 8-Channel Linea r Repeater 1 Features •1 Low 70 mW/C hannel (Typ) Power Consumption, with Op tion to Power Down Unused Channels • Seamless Link Training Support • Enab les Host ASIC to Meet Front-Port Eye Ma sk Requirements over Longer Reach • A dvanced Configurable Signal Conditionin g I/O – Receive CTLE up to 10 dB at 6 GHz – Linear Output Driver – Varia ble Output Voltage Range up to 1200 mVp -p • Programmable via Pin Selection, EEPROM, or SMBus Interface • Single S upply Voltage: 2.5 V or 3.3 V • −40 °C to 85°C Operating Temperature Rang e • Flow-Thru Layout in 10 mm × 5.5 mm 54-Pin Leadless WQFN Package 2 Appl ications • Front-Port 40G-CR4/SR4/LR4 Link Extension • Backplane 40G-KR4 L ink Extension • SAS/SATA/PCIe Link Ex tension • Other Proprietary High Speed Interfaces up to 12.5 Gbps Simplified Functional Block Diagr.
Keywords DS125BR820, datasheet, pdf, etcTI, Low-Power, 12.5, Gbps, 8-Channel, Linear, Repeater, S125BR820, 125BR820, 25BR820, DS125BR82, DS125BR8, DS125BR, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)