LMX2492-Q1 PLL Datasheet

LMX2492-Q1 Datasheet, PDF, Equivalent


Part Number

LMX2492-Q1

Description

14GHz Low Noise Fractional N PLL

Manufacture

etcTI

Total Page 30 Pages
Datasheet
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LMX2492, LMX2492-Q1
SNAS624B – MARCH 2014 – REVISED MAY 2015
LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation
1 Features
1 -227 dBc/Hz Normalized PLL Noise
• 500 MHz - 14 GHz Wideband PLL
• 3.15 - 5.25 V Charge Pump PLL Supply
• Versatile Ramp / Chirp Generation
• 200 MHz Max Phase Detector Frequency
• FSK / PSK Modulation Pin
• Digital Lock Detect
• Single 3.3 V Supply Capability
• Automotive 125°C Q100 Grade 1 Qualification
• Non-Automotive (LMX2492) Option
2 Applications
• Automotive FMCW Radar
• Military Radar
• Microwave Backhaul
• Test and Measurement
• Satellite Communications
• Wireless Infrastructure
• Sampling Clock for High Speed ADC/DAC
3 Description
The LMX2492/92-Q1 is a low noise 14 GHz
wideband delta-sigma fractional N PLL with ramp and
chirp generation. It consists of a phase frequency
detector, programmable charge pump, and high
frequency input for the external VCO. The
LMX2492/92-Q1 supports a broad and flexible class
of ramping capabilities, including FSK, PSK, and
configurable piecewise linear FM modulation profiles
of up to 8 segments. It supports fine PLL resolution
and fast ramp with up to a 200 MHz phase detector
rate. The LMX2492/92-Q1 allows any of its registers
to be read back. The LMX2492/92-Q1 can operate
with a single 3.3 V supply. Moreover, supporting up to
5.25 V charge pump can eliminate the need of
external amplifier, leading to a simpler solution with
improved phase noise performance.
Device Information
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMX2492-Q1RTW WQFN (24)
4.00 mm x 4.00 mm
LMX2492RTW WQFN (24)
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
OSCin
51 :
51 :
GND/OSCin*
GND (x3)
CE
CLK
DATA
LE
2X
MICROWIRE
Interface
TRIG1
TRIG2
MOD
MUXout
MUX
Modulation
Generator
R Divider
(16 bit)
Phase
Comp
N Divider
(18 bit)
6'
Compensation
(24 bit)
Charge
Pump
CPout
C2_LF
Vcp C1_LF
Vcc (x5)
R2_LF
Fin 18 :
36 :
Fin*
51 :
68 :
18 :
18 : To Circuit
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMX2492-Q1
LMX2492, LMX2492-Q1
SNAS624B – MARCH 2014 – REVISED MAY 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings................................... 4
7.2 Storage Conditions.................................................... 4
7.3 ESD Ratings ............................................................ 4
7.4 Recommended Operating Conditions....................... 4
7.5 Thermal Information ................................................. 4
7.6 Electrical Characteristics .......................................... 5
7.7 Timing Requirements, Programming Interface (CLK,
DATA, LE) .................................................................. 6
7.8 Typical Characteristics ............................................. 7
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 13
8.5 Programming........................................................... 14
8.6 Register Map........................................................... 14
8.7 Register Field Descriptions ..................................... 18
8.8 Lock Detect and Charge Pump Monitoring............. 21
8.9 TRIG1,TRIG2,MOD, and MUXout Pins .................. 22
8.10 Ramping Functions ............................................... 24
8.11 Individual Ramp Controls ...................................... 26
9 Applications and Implementation ...................... 27
9.1 Application Information............................................ 27
9.2 Typical Applications ................................................ 27
10 Power Supply Recommendations ..................... 33
11 Layout................................................................... 34
11.1 Layout Guidelines ................................................. 34
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1 Device Support .................................................... 35
12.2 Documentation Support ....................................... 35
12.3 Related Links ........................................................ 35
12.4 Community Resources.......................................... 35
12.5 Trademarks ........................................................... 35
12.6 Electrostatic Discharge Caution ............................ 35
12.7 Glossary ................................................................ 35
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
5 Revision History
Changes from Revision A (June 2014) to Revision B
Page
• Changed Changed CLK, DATA, and LE to right Input/Output Format .................................................................................. 3
• Changed terminal to pin ........................................................................................................................................................ 3
• Changed Same specs, but new format tables for storage and ESD Ratings ....................................................................... 4
• Changed TYP to NOM ........................................................................................................................................................... 4
• Added Added comment for lower voltage operation. ............................................................................................................. 5
• Changed Fixed Diagram. A14 is hightest bit .......................................................................................................................... 6
• Added note in Applications and Implementation section ..................................................................................................... 27
Changes from Original (March 2014) to Revision A
Page
• Changed from 35 to 10........................................................................................................................................................... 6
• Changed from 10 to 4............................................................................................................................................................. 6
• Changed from 10 to 4............................................................................................................................................................. 6
• Changed from 25 to 10 .......................................................................................................................................................... 6
• Changed from 25 t o10........................................................................................................................................................... 6
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 LM X2492/LMX2492-Q1 14 GHz Low Noise Fract ional N PLL with Ramp/Chirp Generation 1 Features •1 -227 dBc/Hz Normalized PLL Noise • 500 MHz - 14 GHz Wideban d PLL • 3.15 - 5.25 V Charge Pump PLL Supply • Versatile Ramp / Chirp Gene ration • 200 MHz Max Phase Detector F requency • FSK / PSK Modulation Pin Digital Lock Detect • Single 3.3 V Supply Capability • Automotive 125° C Q100 Grade 1 Qualification • Non-Au tomotive (LMX2492) Option 2 Application s • Automotive FMCW Radar • Militar y Radar • Microwave Backhaul • Test and Measurement • Satellite Communic ations • Wireless Infrastructure • Sampling Clock for High Speed ADC/DAC 3 Description The LMX2492/92-Q1 is a lo w noise 14 GHz wideband delta-sigma fra ctional N PLL with ramp and chirp gener ation. It consists of a phase frequency detector, programmable charge pump, and high frequency input f.
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