LM4310 Deserializer Datasheet

LM4310 Datasheet, PDF, Equivalent


Part Number

LM4310

Description

RGB Display Differential Interface Deserializer

Manufacture

National Semiconductor

Total Page 14 Pages
Datasheet
Download LM4310 Datasheet


LM4310
May 12, 2008
LM4310
Mobile Pixel Link Two (MPL-2), RGB Display Differential
Interface Deserializer
General Description
Features
The LM4310 deserializes a Two Data + Clock Mobile Pixel
Link (MPL-2) RGB serial link. Two operating modes are sup-
ported: 24-bit RGB and also 18-bit RGB.
The video interconnect is reduced from 28 signals to 3 differ-
ential signals with the LM4312 SER and companion LM4310
DES device, easing flex interconnect design, size constraints
and cost.
24-bit or 18-bit RGB Display Interface
Supports QVGA to > 640 x 480 VGA Resolutions
MPL-2 Differential Physical Layer
Internal 100 Ω Termination and CM Filter
Glitch filter on control signals (DE, VS & HS)
Parity / Payload error reporting pin and data re-circulator
Bufferless displays from QVGA (320 x 240) up to >VGA (640
x 480) pixels are supported.
The Deserializer also provides a glitch filter on the three con-
trol signals (DE, VS and HS). Glitches of 1 or 2 PCLKs wide
are filtered out by the Deserializer to prevent flicker on the
display.
Low Power Consumption
Receiver output drive strength control (RDS)
Frame Sequence bits automatically resync upon data or
clock error
Power down mode reduces power to < 10 µA
Performance of the serial link can be checked by use of the System Benefits
parity/packet error reporting pin that monitors the serial pay-
load odd parity bit and reports errors.
The LM4310 DES and LM4312 SER implements the physical
layer of the MPL-2 Interface and features robust common-
Datasheet.Livemodenoiserejection.
Small Robust Interface
Low Power and Low EMI
24-bit Color Transport
Typical Application Diagram - Bridge Chips - 24-bit to 18-bit RGB Interface
Ordering Information
NSID
LM4310
Package Type
48L LLP, 6mm x 6mm x 0.4mm, 0.4mm pitch
© 2008 National Semiconductor Corporation 202032
20203201
Package ID
TBD
www.national.com

LM4310
Pin Descriptions
Pin Name
No.
of Pins
MPL-2 SERIAL BUS PINS
DD0P, DD0M,
DD1P, DD1M
4
DCP, DCM
2
CONFIGURATION PINS
PD* 1
TM 1
RES0
RDS
2
1
Mode24
1
PE 1
I/O, Type
Description
RGB Deserializer
I, MPL-2
I, MPL-2
MPL-2 Differential Data Receiver True (Plus) and Compliment (Minus) Inputs
Channel 0 and 1
MPL-2 Differential Clock Receiver True (Plus) and Compliment (Minus) Inputs
I,
LVCMOS
I
LVCMOS
I
LVCMOS
I
LVCMOS
I
LVCMOS
O
LVCMOS
Power Down Mode Input
PD* = Low, DES is in SLEEP mode
PD* = High, DES is Enabled
Test Mode
L = Normal Mode, tie to GND
H = Test Mode (Reserved)
Tie to GND
Receiver Drive Strength Control
L = Low Drive Strength --- Use for < 10 MHz operations to reduce EMI
H = Increased Drive Strength — Recommended
Mode 24 bit Select
L = 18-bit RGB
H = 24-bit RGB
Parity / Packet Error Reporting Pin
L = no error (Pass)
H = Packet or Parity Error detected, last known good Pixel Data is re-circulated.
VIDEO INTERFACE PINS
PCLK
1
R[7:0]
G[7:0]
B[7:0]
VS
24
1
HS 1
DE 1
POWER/GROUND PINS
VDD
7
VSS DAP
O,
LVCMOS
O,
LVCMOS
O,
LVCMOS
O,
LVCMOS
O,
LVCMOS
Pixel Clock Output
Video Signals are latched on the RISING edge.
RGB Data Bus Outputs
24-bit Mode - use RGB[7:0, Bit 7 is MSB]
18-bit Mode - use RGB[5:0], RGB[7:6] = NC, LSB aligned.
Vertical Sync. Output
Signal must be greater than 2 PCLKs wide to pass.
Horizontal Sync. Output
Signal must be greater than 2 PCLKs wide to pass.
Data Enable Output
Signal must be greater than 2 PCLKs wide to pass.
Power
Ground
Power Supply Pins. All VDD pins must be connect to power supply.
1.6V to 2.0V
Ground Pin
Note:
I = Input, O = Output, IO = Input/Output. Do not float unused input pins.
www.national.com
2


Features LM4310 Mobile Pixel Link Two (MPL-2), RG B Display Differential Interface Deseri alizer May 12, 2008 LM4310 Mobile Pix el Link Two (MPL-2), RGB Display Differ ential Interface Deserializer General Description Features The LM4310 deser ializes a Two Data + Clock Mobile Pixel Link (MPL-2) RGB serial link. Two oper ating modes are supported: 24-bit RGB a nd also 18-bit RGB. The video interconn ect is reduced from 28 signals to 3 dif ferential signals with the LM4312 SER a nd companion LM4310 DES device, easing flex interconnect design, size constrai nts and cost. ■ 24-bit or 18-bit RGB Display Interface ■ Supports QVGA to > 640 x 480 VGA Resolutions ■ MPL-2 Differential Physical Layer ■ Interna l 100 Ω Termination and CM Filter ■ Glitch filter on control signals (DE, V S & HS) ■ Parity / Payload error repo rting pin and data re-circulator Buffe rless displays from QVGA (320 x 240) up to >VGA (640 x 480) pixels are support ed. The Deserializer also provides a glitch filter on the three control sign.
Keywords LM4310, datasheet, pdf, National Semiconductor, RGB, Display, Differential, Interface, Deserializer, M4310, 4310, 310, LM431, LM43, LM4, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)