7007L RAM Datasheet

7007L Datasheet, PDF, Equivalent


Part Number

7007L

Description

HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

Manufacture

Renesas

Total Page 23 Pages
Datasheet
Download 7007L Datasheet


7007L
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
7007L
Features
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in a 68-pin PLCC and a 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
CEL
R/WL
OER
CER
R/WR
I/O0L- I/O7L
BUSYL(1,2)
A14L
A0L
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
R/WL
15
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
15
SEML
INTL(2)
M/S
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
1
Address
Decoder
CER
OER
R/WR
I/O0R-I/O7R
BUSYR(1,2)
A14R
A0R
SEMR
INTR(2)
2940 drw 01
SEPTEMBER 2019
DSC 2940/16

7007L
7007L
High-Speed 32K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
featurecontrolledby CEpermitstheon-chipcircuitryofeachporttoenter
a very LOW standby power mode.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 850mW of power.
The IDT7007 is packaged in a 68-pin PLCC and an 80-pin thin
quad flatpack TQFP.
Pin Configurations(1,2,3)
I/O7R
N/C
OER
R/WR
SEMR
CER
A14R
A13R
GND
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
27 9
28 8
29 7
30 6
31 5
32 4
33 3
34
7007
PLG68(4)
2
35 1
36
68-Pin PLCC
68
37
Top View
67
38 66
39 65
40 64
41 63
42 62
4344 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
A14L
A13L
VCC
A12L
A11L
A10L
A9L
A8L
A7L
A6L
2940 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
2


Features HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM 7007L Features ◆ True Dual-Ported m emory cells which allow simultaneous re ads of the same memory location ◆ Hig h-speed access – Commercial: 15ns (ma x.) – Industrial: 20ns (max.) ◆ Low -power operation – IDT7007L Active: 8 50mW (typ.) Standby: 1mW (typ.) ◆ IDT 7007 easily expands data bus width to 1 6 bits or more using the Master/Slave s elect when cascading more than one devi ce ◆ M/S = H for BUSY output flag on Master, M/S = L for BUSY input on Slav e ◆ Interrupt Flag ◆ On-chip port a rbitration logic ◆ Full on-chip hardw are support of semaphore signaling betw een ports ◆ Fully asynchronous operat ion from either port ◆ TTL-compatible , single 5V (±10%) power supply ◆ Av ailable in a 68-pin PLCC and a 80-pin T QFP ◆ Industrial temperature range ( 40°C to +85°C) is available for sel ected speeds ◆ Green parts available, see ordering information Functional B lock Diagram OEL CEL R/WL OER CER R/WR I/O0L- I/O7L BUSYL(1,2) A14L A0L I/O Control I/O Control.
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