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UCC3580-1

Texas Instruments
Part Number UCC3580-1
Manufacturer Texas Instruments
Description Single Ended Active Clamp/Reset PWM
Published Jan 3, 2020
Detailed Description Single Ended Active Clamp/Reset PWM UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 FEATURES Provides Auxilia...
Datasheet PDF File UCC3580-1 PDF File

UCC3580-1
UCC3580-1

Overview
Single Ended Active Clamp/Reset PWM UCC1580-1,-2,-3,-4 UCC2580-1,-2,-3,-4 UCC3580-1,-2,-3,-4 FEATURES Provides Auxiliary Switch Activation Complementary to Main Power Switch Drive Programmable deadtime (Turn-on Delay) Between Activation of Each Switch Voltage Mode Control with Feedforward Operation Programmable Limits for Both Transformer Volt- Second Product and PWM Duty Cycle High Current Gate Driver for Both Main and Auxiliary Outputs Multiple Protection Features with Latched Shutdown and Soft Restart Low Supply Current (100 mA Startup, 1.
5 mA Operation) DESCRIPTION The UCC3580 family of PWM controllers is designed to implement a variety of active clamp/reset and synchronous rectifier switching converter topologies.
While containing all the necessary functions for fixed frequency, high performance pulse width modulation, the additional feature of this design is the inclusion of an auxiliary switch driver which complements the main power switch, and with a programmable deadtime or delay between each transition.
The active clamp/reset technique allows operation of single ended converters beyond 50% duty cycle while reducing voltage stresses on the switches, and allows a greater flux swing for the power transformer.
This approach also allows a reduction in switching losses by recovering energy stored in parasitic elements such as leakage inductance and switch capacitance.
The oscillator is programmed with two resistors and a capacitor to set switching frequency and maximum duty cycle.
A separate synchronized ramp provides a voltage feedforward pulse width modulation and a programmed maximum volt-second limit.
The generated clock from the oscillator contains both frequency and maximum duty cycle information.
(continued) BLOCK DIAGRAM Pin Numbers refer to DIL-16 and SOIC-16 packages SLUS292D - FEBRUARY 1999 - REVISED FEBRUARY 2007 UDG-95069-2 DESCRIPTION (cont.
) The main gate drive output (OUT1) is controlled by the pulse width modulator.
The second output (OUT...


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