PA7536 Logic Datasheet

PA7536 Datasheet, PDF, Equivalent


Part Number

PA7536

Description

Programmable Electrically Erasable Logic

Manufacture

ICT

Total Page 10 Pages
Datasheet
Download PA7536 Datasheet


PA7536
Commercial/Industrial
PA7536 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
High-Speed Commercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmer
General Description
The PA7536 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on ICT’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7536 offers
versatile logic array architecture with 12 I/O pins, 14 input
pins and 36 registers/latches (12 buried logic cells, 12
Input registers/latches and 12 buried registers/latches). Its
logic array implements 50 sum-of-products logic functions
that share 64 product terms. The PA7536’s logic and I/O
cells (LCCs, IOCs) are extremely flexible offering up to
three output functions per cell (a total of 36 for all 12 logic
cells). Cells are configurable as D, T, and JK registers with
independent or global clocks, resets, presets, clock
polarity, and other special features, making the PA7536
suitable for a variety of combinatorial, synchronous and
asynchronous logic applications. The PA7536 offers pin
compatibility and super-set functionality to popular 28-pin
PLDs, such as the 26V12. Thus, designs that exceed the
architectures of such devices can be expanded upon. The
PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
and 83.3MHz (fMAX) and moderate power consumption
60mA (45mA typical). Packaging includes 28-pin DIP,
SOIC, and PLCC (see Figure 1). Development and
programming support for the PA7536 is provided by ICT
and popular third-party development tool manufacturers.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/C LK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
1
28 I/C LK2 I/C LK1
1
28 I/C LK2
2
27 I/O
I2
27 I/O
I3
26 I/O
3
26 I/O
I4
25 I/O
4
25 I/O
I5
24 I/O
5
24 I/O
I6
23 I/O
VCC
7
22 I/O
6
23 I/O
I8
21 GND
7
22 I/O
I9
20 I/O
8
21 GND
I 10
19 I/O
I 11
18 I/O
9
20 I/O
I 12
17 I/O
10 19 I/O
I 13
16 I/O
11 18 I/O
I 14
15 I/O
12 17 I/O
13 16 I/O
SO IC/TSSOP
14 15 I/O
D IP
I
I
VCC
I
I
I
I
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
I/O
I/O
I/O
I/O
GND
I/O
I/O
PLCC
08-16-001A
I/CLK1
I
I
I
I
I
VCC
I
I
I
I
I
I
I
2 Input/
Global Clock Pins
12 Input Pins
In p u t
Cells
(IN C )
G lobal Cells
Input Cells
I/O Cells
Logic Control Cells
PA7536
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
G lo ba l
C e lls
76 (38X2)
Array Inputs
true and
2 complement
12 12
I/O
C e lls
(IOC)
12 I/O Pins
L o g ic
Array
12 Buried
logic
Logic
A
B Control
C Cells
D (LCC)
12
Logic functions
to I/O cells
2 sum terms
3 product term s
for Global Cells
48 sum term s
(four per LCC)
12
12 Logic Control Cells
up to 3 output functions per cell
(36 total output functions possible)
08-16-002A
1 04-02-052D

PA7536
Commercial/Industrial
Inside the Logic Array
The heart of the PEELArray architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. Depending on the PEELArray selected, a
range of 38 to 62 inputs is available into the array from the
I/O cells, inputs cells and input/global-clock pins.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
number of product-terms among PEELArrays ranges
from 67 to 125. All product terms (with the exception of
certain ones fed to the global cells) can be programmably
connected to any of the sum-terms of the logic control cells
(four sum-terms per logic control cell). Product-terms and
sum-terms are also routed to the global cells for control
purposes. Figure 3 shows a detailed view of the logic
array structure.
From
IO C ells
(IO C,INC,
I/C L K )
38 Array Inputs
ensures that product-terms are used where they are
needed and not left unutilized or duplicated. Secondly, the
sum-of-products functions provided to the logic cells can
be used for clocks, resets, presets and output enables
instead of just simple product-term control.
The PEELlogic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product
terms to implement 16 exclusive-OR functions. The
PEELlogic array easily handles this in a single level
delay. Other PLDs/CPLDs either run out of product-terms
or require expanders or additional logic levels that often
slow performance and skew timing.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control
the logic functions created in the logic array. Each LCC has
four primary inputs and three outputs. The inputs to each
LCC are complete sum-of-product logic functions from the
array, which can be used to implement combinatorial and
sequential logic functions, and to control LCC registers and
I/O cell output enables.
From Global Cell
System Clock
Preset RegType Reset
From
Logic
C o n tr o l
C e lls
(LCC)
MUX
On/Off
P
D ,T,J
Q
REG
K
R
MUX
To
Array
To
Global
C e lls
67 Product Terms
From
Array
A
B
C
D
To
Logic Control
C e lls
(LCC)
MUX
To
I/O
Cell
08-16-004A
PA7536 Logic Array
50 Sum Term s
Figure 3 PA7536 Logic Array
0 8- 1 6 -0 0 3A
True Product-Term Sharing
The PEELlogic array provides several advantages over
common PLD logic arrays. First, it allows for true product-
term sharing, not simply product-term steering, as
commonly found in other CPLDs. Product term sharing
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with
synchronous or asynchronous D, T, or JK registers
(clocked-SR registers, which are a subset of JK, are also
possible). See Figure 5. EEPROM memory cells are used
for programming the desired configuration. Four sum-of-
product logic functions (SUM terms A, B, C and D) are fed
into each LCC from the logic array. Each SUM term can be
selectively used for multiple functions as listed below.
2 04-02-052D


Features Commercial/Industrial PA7536 PEEL Array ™ Programmable Electrically Erasable Logic Array Versatile Logic Array Arch itecture - 12 I/Os, 14 inputs, 36 regis ters/latches - Up to 36 logic cell outp ut functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal f or Combinatorial, Synchronous and Async hronous Logic Applications - Integratio n of multiple PLDs and random logic - B uried counters, complex state-machines - Comparators, decoders, multiplexers a nd other wide-gate functions High-Speed Commercial and Industrial Versions - A s fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) - Industrial grade available fo r 4.5 to 5.5V VCC and -40 to +85 °C te mperatures CMOS Electrically Erasable Technology - Reprogrammable in 28-pin D IP, SOIC and PLCC packages Flexible Log ic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or globa l clocks, resets, presets, clock polarity and output enables - Sum.
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