SN54273 FLIP-FLOP Datasheet

SN54273 Datasheet, PDF, Equivalent


Part Number

SN54273

Description

OCTAL D-TYPE FLIP-FLOP

Manufacture

etcTI

Total Page 8 Pages
Datasheet
Download SN54273 Datasheet


SN54273
Contains Eight Flip-Flops With Single-Rail
Outputs
Buffered Clock and Direct Clear Inputs
Individual Data Input to Each Flip-Flop
Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Generators
description
These monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear input.
Information at the D inputs meeting the setup time
requirements is transferred to the Q outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock input is at
either the high or low level, the D input signal has
no effect ar the output.
These flip-flops are guaranteed to respond to
clock frequencies ranging form 0 to 30 megahertz
while maximum clock frequency is typically 40
megahertz. Typical power dissipation is 39
milliwatts per flip-flop for the 273 and 10 milliwatts
for the LS273.
SN54273, SN54LS273, SN74273, SN74LS273
OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988
SN54273, SN74LS273 . . . J OR W PACKAGE
SN74273 . . . N PACKAGE
SN74LS273 . . . DW OR N PACKAGE
(TOP VIEW)
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
SN54LS273 . . . FK PACKAGE
(TOP VIEW)
2D
3 2 1 20 19
4 18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
FUNCTION TABLE
(each flip-flop)
INPUTS
CLEAR CLOCK D
OUTPUT
Q
L
XX
L
H
H
H
H L L
H
LX
Q0
logic symbol
CLR
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
EN
C1
1D
2
1Q
5
2Q
6
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
This symbol is in accordance with ANSI/IEEE Std.
91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DW, J, N, and W packages.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1988, Texas Instruments Incorporated
1

SN54273
SN54273, SN54LS273, SN74273, SN74LS273
OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC
Req
273
INPUT
TYPICAL OF ALL OUTPUTS
100
NOM
VCC
OUTPUT
Clear: Req = 3 kNOM
Clock: Req = 6 kNOM
All other inputs: Req = 8 kNOM
EQUIVALENT OF EACH INPUT
LS273
VCC
INPUT
20 k
NOM
TYPICAL OF ALL OUTPUTS
VCC
120 NOM
OUTPUT
logic diagram (positive logic)
CLOCK 11
1D 2D 3D 4D 5D 6D 7D 8D
3 4 7 8 13 14 17 18
1D 1D 1D 1D 1D 1D 1D 1D
C1 C1 C1 C1 C1 C1 C1 C1
R RRRRRRR
1
CLEAR
2 5 6 9 12 15 16 19
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
Pin numbers shown are for the DW, J, N, and W packages.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features • Contains Eight Flip-Flops With Singl e-Rail Outputs • Buffered Clock and D irect Clear Inputs • Individual Data Input to Each Flip-Flop • Application s Include: Buffer/Storage Registers Shi ft Registers Pattern Generators descrip tion These monolithic, positive-edge-tr iggered flipflops utilize TTL circuitry to implement D-type flip-flop logic wi th a direct clear input. Information at the D inputs meeting the setup time re quirements is transferred to the Q outp uts on the positive-going edge of the c lock pulse. Clock triggering occurs at a particular voltage level and is not d irectly related to the transition time of the positive-going pulse. When the c lock input is at either the high or low level, the D input signal has no effec t ar the output. These flip-flops are g uaranteed to respond to clock frequenci es ranging form 0 to 30 megahertz while maximum clock frequency is typically 4 0 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ′273 and 10 milliwatts for the ′.
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