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74LS374 FLIP-FLOP Datasheet |
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| Part Number | 74LS374 |
| Description | OCTAL D-TYPE FLIP-FLOP |
| Manufacture | Motorola |
| Total Page | 7 Pages |
| Datasheet |
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus
organized system applications. The flip-flops appear transparent to the data
(data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is
LOW, the data that meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop fea-
turing separate D-type inputs for each flip-flop and 3-state outputs for bus ori-
ented applications. A buffered Clock (CP) and Output Enable (OE) is common
to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low
Power Schottky technology and is compatible with all Motorola TTL families.
• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
D0 – D7
LE
CP
OE
O0 – O7
Data Inputs
Latch Enable (Active HIGH) Input
Clock (Active HIGH going edge) Input
Output Enable (Active LOW) Input
Outputs (Note b)
LOADING (Note a)
HIGH
LOW
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 (25) U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 (7.5) U.L.
NOTES:
a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
(74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and
65 U.L. for Commercial (74) Temperature Ranges.
SN54/74LS373
SN54/74LS374
OCTAL TRANSPARENT LATCH
WITH 3-STATE OUTPUTS;
OCTAL D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUT
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN54 / 74LS373
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54 / 74LS374
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
VCC O7 D7 D6 O6 O5 D5 D4 O4 CP
20 19 18 17 16 15 14 13 12 11
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
NOTE:
1 2 3 4 5 6 7 8 9 10
The Flatpak version
has the same pinouts
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
(Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-521
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SN54/74LS373 • SN54/74LS374
LS373
Dn LE OE On
H H LH
TRUTH TABLE
L HL
X LL
X XH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
L
Q0
Z*
* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
Dn
H
L
X
LS374
LE OE
L
L
XH
On
H
L
Z*
LOGIC DIAGRAMS
SN54LS / 74LS373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
LATCH
ENABLE
11 LE
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
OE
1
O0
2
O1
5
O2
6
O3
9
O4
12
O5
15
O6
16
O7
19
SN54LS / 74LS374
3
11 D0
CP
CP D
QQ
4
D1
CP D
QQ
7
D2
CP D
QQ
8
D3
CP D
QQ
13
D4
CP D
QQ
14
D5
CP D
QQ
17
D6
CP D
QQ
18
D7
CP D
QQ
OE
1
O0 O1 O2
O3 O4
O5 O6
O7
256
9 12 15 16 19
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54
– 1.0
mA
74 – 2.6
54 12 mA
74 24
FAST AND LS TTL DATA
5-522
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| Features | OCTAL TRANSPARENT LATCH WITH 3-STATE OUT PUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STA TE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs f or bus organized system applications. T he flip-flops appear transparent to the data (data changes asynchronously) whe n Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup tim es is latched. Data appears on the bus when the Output Enable (OE) is LOW. Whe n OE is HIGH the bus output is in the h igh impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-typ e Flip-Flop featuring separate D-type i nputs for each flip-flop and 3-state ou tputs for bus oriented applications. A buffered Clock (CP) and Output Enable ( OE) is common to all flip-flops. The SN 54 / 74LS374 is manufactured using adva nced Low Power Schottky technology and is compatible with all Motorola TTL fam ilies. • Eight Latches in a Single Pa ckage • 3-State Outputs for Bus Inter facing • Hysteresis on Latch Enable • Edge-Triggered D-Type Inputs . |
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