8T349316 Buffer Datasheet

8T349316 Datasheet, PDF, Equivalent


Part Number

8T349316

Description

2.5V LVDS 1:16 Clock Fanout Buffer

Manufacture

Renesas

Total Page 20 Pages
Datasheet
Download 8T349316 Datasheet


8T349316
2.5V LVDS 1:16 Clock Fanout Buffer
8T349316
DATASHEET
General Description
The 8T349316 is a 2.5V differential clock buffer with sixteen LVDS
outputs. The fanout from a differential input to the sixteen LVDS
outputs reduces loading on the preceding driver and provides an
efficient clock distribution network. The 8T349316 can act as a
translator from a differential HSTL, LVPECL, CML or LVDS input to
LVDS output signals. A single-ended 3.3V, 2.5V LVCMOS/LVTTL
input can also be used to translate to LVDS outputs. The redundant
input capability allows for an asynchronous change-over from a
primary clock source to a secondary clock source. Selectable
reference inputs are controlled by SEL. The 8T349316 outputs can
be asynchronously enabled/disabled. When disabled, the outputs
will drive to the value selected by the GL pin. Multiple power and
grounds reduce noise.The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
Clock signal selection and fanout to 16 LVDS outputs
Guaranteed Low Skew < 50ps (max)
Low output pulse skew < 125ps (max)
Propagation delay < 1.75ns (max)
Up to 1GHz clock signal operation
Support the following input types: HSTL, LVPECL, HCSL, LVTTL
Selectable differential input
Power-down mode
Full 2.5V power supply
-40°C to +85°C ambient operating temperature
Lead-free (RoHS 6) 52-lead VFQFN-P packaging
Replacement device for the 5T9316
Block Diagram
A1
1
nA1
A2
0
nA2
SEL
GL
nG1
nG2
nPD
POWER DOWN
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
OUT
CTRL
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
Q10
nQ10
Q11
nQ11
Q12
nQ12
Q13
nQ14
Q15
nQ15
Q16
nQ16
Pin Assignment
nG1
VDD
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
VDD
A1
nA1
52 51 50 49 48 47 46 45 44 43 42 41 40
1 39
2 38
3 37
4 36
5 35
6 34
7
8T349316
33
8 32
9 31
10 30
11 29
12 28
13 27
14 15 16 17 17 19 20 21 22 23 24 25 26
nG2
VDD
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
VDD
A2
nA2
52-lead VFQFN-P, EPad
8mm x 8mm x 0.9mm Package body
NL package
Top View
8T349316 REVISION 2 11/2/14
1 ©2014 Integrated Device Technology, Inc.

8T349316
8T349316 DATASHEET
Pin Description and Pin Characteristic Tables
Table 1: Pin Descriptions
Number
Name
1 nG1
2 VDD
3 Q1
4 nQ1
5 Q2
6 nQ2
7 Q3
8 nQ3
9 Q4
10 nQ4
11 VDD
12 A1
13 nA1
14 GL
15 VDD
16 Q5
17 nQ5
18 Q6
19 nQ6
20 Q7
21 nQ7
22 Q8
23 nQ8
24 VDD
25 GND
26 nc
27 nA2
28 A2
29 VDD
30 nQ9
31 Q9
32 nQ10
33 Q10
34 nQ11
Type
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Input
Input
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
-
Input
Input
Power
Output
Output
Output
Output
Output
-
-
-
-
-
-
-
Description
Output enable control input for the Q[1:8] differential outputs.
See Table 3C. LVCMOS/LVTTL interface levels.
Positive power supply voltage.
Differential clock output Q1. LVDS interface signals.
Differential clock output Q1. LVDS interface signals.
Differential clock output Q2. LVDS interface signals.
Differential clock output Q2. LVDS interface signals.
Differential clock output Q3. LVDS interface signals.
Differential clock output Q3. LVDS interface signals.
Differential clock output Q4. LVDS interface signals.
Differential clock output Q4. LVDS interface signals.
Positive power supply voltage.
Differential clock signal input 1.
Differential clock signal input 1.
Control input for the output level for outputs in disable state.
See Table 3C and Table 3D. LVCMOS/LVTTL interface levels.
Positive power supply voltage.
Differential clock output Q5. LVDS interface signals.
Differential clock output Q5. LVDS interface signals.
Differential clock output Q6. LVDS interface signals.
Differential clock output Q6. LVDS interface signals.
Differential clock output Q7. LVDS interface signals.
Differential clock output Q7. LVDS interface signals.
Differential clock output Q8. LVDS interface signals.
Differential clock output Q8. LVDS interface signals.
Positive power supply voltage.
Power Supply Ground.
Not connected. It is recommended to connect this pin to board GND (0V).
Differential clock signal input 2.
Differential clock signal input 2.
Positive power supply voltage.
Differential clock output Q9. LVDS interface signals.
Differential clock output Q9. LVDS interface signals.
Differential clock output Q10. LVDS interface signals.
Differential clock output Q10. LVDS interface signals.
Differential clock output Q11. LVDS interface signals.
2.5V LVDS 1:16 CLOCK FANOUT BUFFER
2
REVISION 2 11/2/14


Features 2.5V LVDS 1:16 Clock Fanout Buffer 8T34 9316 DATASHEET General Description Th e 8T349316 is a 2.5V differential clock buffer with sixteen LVDS outputs. The fanout from a differential input to the sixteen LVDS outputs reduces loading o n the preceding driver and provides an efficient clock distribution network. T he 8T349316 can act as a translator fro m a differential HSTL, LVPECL, CML or L VDS input to LVDS output signals. A sin gle-ended 3.3V, 2.5V LVCMOS/LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for an asynchronous change-over from a primary clock source to a secon dary clock source. Selectable reference inputs are controlled by SEL. The 8T34 9316 outputs can be asynchronously enab led/disabled. When disabled, the output s will drive to the value selected by t he GL pin. Multiple power and grounds r educe noise.The extended temperature ra nge supports wireless infrastructure, t elecommunication and networking end equipment requirements. The.
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