ICS9DB108 Buffer Datasheet

ICS9DB108 Datasheet, PDF, Equivalent


Part Number

ICS9DB108

Description

Eight Output Differential Buffer

Manufacture

Renesas

Total Page 17 Pages
Datasheet
Download ICS9DB108 Datasheet


ICS9DB108
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Eight Output Differential Buffer for PCI-Express
Recommended Application:
Pin Configuration
DB800 Intel Yellow Cover part with PCI-Express support.
SRC_DIV# 1
48 VDDA
Output Features:
• 8 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
VDD
GND
SRC_IN
SRC_IN#
OE_0
2
3
4
5
6
47 GNDA
46 IREF
45 LOCK
44 OE_7
43 OE_4
Key Specifications:
• Outputs cycle-cycle jitter < 50ps
r• Outputs skew: 50ps
• +/- 300ppm frequency accuracy on output clocks
foFeatures/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
d• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
e• Supports undriven differential output pair in PD# and
Not recnoemwmdeensdignsSRC_STOP# for power management.
OE_3 7
DIF_0 8
DIF_0# 9
GND 10
VDD 11
DIF_1 12
DIF_1# 13
OE_1 14
OE_2 15
DIF_2 16
DIF_2# 17
GND 18
VDD 19
DIF_3 20
DIF_3# 21
BYPASS#/PLL 22
SCLK 23
SDATA 24
42 DIF_7
41 DIF_7#
40 GND
39 VDD
38 DIF_6
37 DIF_6#
36 OE_6
35 OE_5
34 DIF_5
33 DIF_5#
32 GND
31 VDD
30 DIF_4
29 DIF_4#
28 HIGH_BW#
27 SRC_STOP#
26 PD#
25 GND
48-pin SSOP & TSSOP
0723G—12/02/08

ICS9DB108
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Pin Description
PIN # PIN NAME
1 SRC_DIV#
2 VDD
3 GND
4 SRC_IN
5 SRC_IN#
6 OE_0
7 OE_3
8 DIF_0
9 DIF_0#
10 GND
11 VDD
12 DIF_1
13 DIF_1#
14 OE_1
15 OE_2
16 DIF_2
17 DIF_2#
18 GND
19 VDD
20 DIF_3
21 DIF_3#
22 BYPASS#/PLL
23 SCLK
24 SDATA
PIN TYPE
DESCRIPTION
IN
PWR
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
I/O
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
0723G—12/02/08
2


Features Integrated Circuit Systems, Inc. ICS9DB 108 (Not recommended for new designs) Eight Output Differential Buffer for PC I-Express Recommended Application: Pi n Configuration DB800 Intel Yellow Cov er part with PCI-Express support. SRC_ DIV# 1 48 VDDA Output Features: • 8 - 0.7V current-mode differential outpu t pairs • Supports zero delay buffer mode and fanout mode • Bandwidth prog ramming available VDD GND SRC_IN SRC_I N# OE_0 2 3 4 5 6 47 GNDA 46 IREF 45 LOCK 44 OE_7 43 OE_4 Key Specification s: • Outputs cycle-cycle jitter < 50p s r• Outputs skew: 50ps • +/- 300pp m frequency accuracy on output clocks f oFeatures/Benefits: • Supports tight ppm accuracy clocks for Serial-ATA d• Spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% cen ter spread e• Supports undriven diffe rential output pair in PD# and Not recn oemwmdeensdignsSRC_STOP# for power mana gement. OE_3 7 DIF_0 8 DIF_0# 9 GND 10 VDD 11 DIF_1 12 DIF_1# 13 OE_1 14 OE_2 15 DIF_2 16 DIF_2# 17 GND 18 VDD 19 DIF_3.
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