9DB202 Attenuator Datasheet

9DB202 Datasheet, PDF, Equivalent


Part Number

9DB202

Description

PCI Express Jitter Attenuator

Manufacture

Renesas

Total Page 14 Pages
Datasheet
Download 9DB202 Datasheet


9DB202
PCI Express Jitter Attenuator
9DB202
Data Sheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
GENERAL DESCRIPTION
FEATURES
The 9DB202 is a high perfromance 1-to-2 Differential-to-HCSL
Jitter Attenuator designed for use in PCI Express™ systems. In
some PCI Express™ systems, such as those found in desktop PCs,
the PCI Express™ clocks are generated from a low bandwidth,
high phase noise PLL frequency synthesizer. In these systems, a
jitter-attenuating device may be necessary in order to reduce high
frequency random and deterministic jitter components from the PLL
synthesizer and from the system board. The 9DB202 has two PLL
bandwidth modes. In low bandwidth mode, the PLL loop bandwidth
is 500kHz. This setting offers the best jitter attenuation and is still
high enough to pass a triangular input spread spectrum profile. In
high bandwidth mode, the PLL bandwidth is at 1MHz and allows
the PLL to pass more spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can
be set for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1).
Two 0.7V current mode differential HCSL output pairs
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Input frequency range: 90MHz - 140MHz
VCO range: 450MHz - 700MHz
Output skew: 110ps (maximum)
Cycle-to-cycle jitter: 110ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in lead-free RoHS compliant package
BLOCK DIAGRAM
IREF
+-
Current
Set
Industrial temperature information available upon request
For functional replacement use 8714004
PIN ASSIGNMENT
nOE0
1 HiZ
0 Enabled
nCLK
CLK
BYPASS
nOE1
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
1 HiZ
0 Enabled
0 ÷4
1 ÷5
0
1
FS0
0 ÷5
1 ÷4
0
1
FS1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
9DB202
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
package body
G Package
Top View
9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision B March 11, 2016

9DB202
9DB202 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1 PLL_BW Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
2 CLK Input Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. V /2 default when left floating.
DD
4 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
5, 9, 12, 16
6, 15
V
DD
GND
Power
Power
Core supply pins.
Power supply ground.
7, 8
PCIEXT0,
PCIEXC0
Output
Differential output pairs. HCSL interface levels.
10, 11
nOE0, nOE1
Input
Pulldown
Output enable. When HIGH, forces outputs to HiZ state.
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
13, 14
PCIEXC1,
PCIEXT1
Output
Differential output pairs. HCSL interface levels.
17 FS1 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
18
IREF
Input
A fixed precision resistor (475Ω) from this pin to ground provides a refer-
ence current used for differential current-mode PCIEX clock outputs.
19
BYPASS
Power
Pulldown
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.
LVCMOS/LVTTL interface levels.
20 V Power
DDA
Analog supply pin. Requires 24Ω series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs Outputs
FS0 PCIEX0
0 5/4
11
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs Outputs
FS1 PCIEX1
01
1 5/4
TABLE 3C. BYPASS TABLE
Inputs
BYPASS
0
1
Mode
PLL Mode
Bypass Mode
(output = inputs)
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, NOE0
Inputs Outputs
nOE0
PCIEX0
0 Enabled
1 HiZ
TABLE 3E. OUTPUT ENABLE
FUNCTION TABLE, NOE1
Inputs Outputs
nOE1
PCIEX1
0 Enabled
1 HiZ
TABLE 3F. PLL BANDWIDTH TABLE
Inputs
Bandwidth
PLL_BW
0 500kHz
1 1MHz
©2016 Integrated Device Technology, Inc
2
Revision B March 11, 2016


Features PCI Express Jitter Attenuator 9DB202 Da ta Sheet PRODUCT DISCONTINUATION NOTIC E - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 GENERAL DESCRIPTION FEATURES Th e 9DB202 is a high perfromance 1-to-2 D ifferential-to-HCSL Jitter Attenuator d esigned for use in PCI Express™ syste ms. In some PCI Express™ systems, suc h as those found in desktop PCs, the PC I Express™ clocks are generated from a low bandwidth, high phase noise PLL f requency synthesizer. In these systems, a jitter-attenuating device may be nec essary in order to reduce high frequenc y random and deterministic jitter compo nents from the PLL synthesizer and from the system board. The 9DB202 has two P LL bandwidth modes. In low bandwidth mo de, the PLL loop bandwidth is 500kHz. T his setting offers the best jitter atte nuation and is still high enough to pas s a triangular input spread spectrum pr ofile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PL L to pass more spread spectrum modulation. For serdes which have x10 re.
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