SN54HC03 GATES Datasheet

SN54HC03 Datasheet, PDF, Equivalent


Part Number

SN54HC03

Description

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Manufacture

etcTI

Total Page 20 Pages
Datasheet
Download SN54HC03 Datasheet


SN54HC03
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
SN54HC03, SN74HC03
QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES
WITH OPENĆDRAIN OUTPUTS
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003
D Typical tpd = 8 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
SN54HC03 . . . J OR W PACKAGE
SN74HC03 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HC03 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
1Y
3 2 1 20 19
4 18
4A
NC 5
17 NC
2A 6
16 4Y
NC 7
15 NC
2B 8
14 3B
9 10 11 12 13
description/ordering information
NC − No internal connection
The ’HC03 devices contain four independent 2-input NAND gates. They perform the Boolean function
Y = A B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to perform correctly. They
may be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND
functions.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC03N
SN74HC03N
Tube of 50
SN74HC03D
−40°C to 85°C
SOIC − D
SOP − NS
Reel of 2500
Reel of 250
Reel of 2000
SN74HC03DR
SN74HC03DT
SN74HC03NSR
HC03
HC03
TSSOP − PW
Tube of 90
Reel of 2000
SN74HC03PW
SN74HC03PWR
HC03
CDIP − J
Tube of 25
SNJ54HC03J
SNJ54HC03J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC03W
SNJ54HC03W
LCCC − FK
Tube of 55
SNJ54HC03FK
SNJ54HC03FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54HC03
SN54HC03, SN74HC03
QUADRUPLE 2ĆINPUT POSITIVEĆNAND GATES
WITH OPENĆDRAIN OUTPUTS
SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HH
L
LX
H
XL
H
logic diagram (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC03
MIN NOM MAX
SN74HC03
UNIT
MIN NOM MAX
VCC Supply voltage
2 5 6 2 5 6V
VCC = 2 V
1.5
1.5
VIH High-level input voltage
VCC = 4.5 V
VCC = 6 V
3.15
4.2
3.15
4.2
V
VCC = 2 V
0.5 0.5
VIL Low-level input voltage
VCC = 4.5 V
VCC = 6 V
1.35 1.35 V
1.8 1.8
VI Input voltage
0
VCC
0
VCC V
VO Output voltage
0
VCC
0
VCC V
VCC = 2 V
1000
1000
t/v Input transition rise/fall time
VCC = 4.5 V
500 500 ns
VCC = 6 V
400 400
TA Operating free-air temperature
−55 125 −40
85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC03, SN74HC03 QUADRUPLE 2 ĆINPUT POSITIVEĆNAND GATES WITH OPEN DRAIN OUTPUTS SCLS077E − MARCH 1984 − REVISED NOVEMBER 2003 D Typical tpd = 8 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max SN54HC0 3 . . . J OR W PACKAGE SN74HC03 . . . D , N, NS, OR PW PACKAGE (TOP VIEW) SN54 HC03 . . . FK PACKAGE (TOP VIEW) VCC 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 1 4 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y 1Y 3 2 1 20 19 4 18 4A NC 5 17 NC 2A 6 16 4Y NC 7 15 NC 2B 8 14 3B 9 10 11 12 13 3A 4B NC NC GND 1A 2Y 1B 3Y description/ordering informa tion NC − No internal connection Th e ’HC03 devices contain four independ ent 2-input NAND gates. They perform th e Boolean function Y = A • B or Y = A + B in positive logic. The open-drain outputs require pullup resistors to per form correctly. They may be connected to other open-drain outputs to implement .
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