SN74LVC2G00W-EP GATE Datasheet

SN74LVC2G00W-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G00W-EP

Description

DUAL 2-INPUT POSITIVE-NAND GATE

Manufacture

etcTI

Total Page 9 Pages
Datasheet
Download SN74LVC2G00W-EP Datasheet


SN74LVC2G00W-EP
www.ti.com
FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –55°C
to 115°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC2G00W-EP
DUAL 2-INPUT POSITIVE-NAND GATE
SCES645 – SEPTEMBER 2005
• ±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
1
2
3
4
8 VCC
7 1Y
6 2B
5 2A
DESCRIPTION/ORDERING INFORMATION
This dual 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G00W-EP performs the Boolean function Y = A B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–55°C to 115°C
SSOP – DCT
PACKAGE (1)
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74LVC2G00WDCTREP
C00_ _ _
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated

SN74LVC2G00W-EP
SN74LVC2G00W-EP
DUAL 2-INPUT POSITIVE-NAND GATE
SCES645 – SEPTEMBER 2005
FUNCTION TABLE
(EACH GATE)
INPUTS
AB
HH
LX
XL
OUTPUT
Y
L
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DCT package
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
220
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2


Features www.ti.com FEATURES • Controlled Basel ine – One Assembly/Test Site, One Fab rication Site • Extended Temperature Performance of –55°C to 115°C • E nhanced Diminishing Manufacturing Sourc es (DMS) Support • Enhanced Product-C hange Notification • Qualification Pe digree (1) • Supports 5-V VCC Operati on • Inputs Accept Voltages to 5.5 V • Max tpd of 5.3 ns at 3.3 V • Low Power Consumption, 10-µA Max ICC (1) C omponent qualification in accordance wi th JEDEC and industry standards to ensu re reliable operation over an extended temperature range. This includes, but i s not limited to, Highly Accelerated St ress Test (HAST) or biased 85/85, tempe rature cycle, autoclave or unbiased HAS T, electromigration, bond intermetallic life, and mold compound life. Such qua lification testing should not be viewed as justifying use of this component be yond specified performance and environm ental limits. SN74LVC2G00W-EP DUAL 2-I NPUT POSITIVE-NAND GATE SCES645 – SEPTEMBER 2005 • ±24-mA Output Drive at 3.3 V • Typic.
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