SN74LVC2G04-EP Gate Datasheet

SN74LVC2G04-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G04-EP

Description

Dual Inverter Gate

Manufacture

etcTI

Total Page 13 Pages
Datasheet
Download SN74LVC2G04-EP Datasheet


SN74LVC2G04-EP
www.ti.com
SN74LVC2G04-EP
DUAL INVERTER GATE
SGLS365 – AUGUST 2006
FEATURES
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Ioff Supports Partial Power-Down-Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Enhanced Product-Change Notification
Qualification Pedigree(1)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
1A
GND
1
2
1A 1 6 1Y
1A 1 6 1Y
2A 3 4 2Y
6
5
1Y
GND
VCC
2A
2
3
5
VCC
GND 2
2A 3
5 VCC
4 2Y
GND 2 5 VCC
1A 1 6 1Y
4 2Y
2A 3
4 2Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G04 performs the Boolean
function Y = A.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated

SN74LVC2G04-EP
SN74LVC2G04-EP
DUAL INVERTER GATE
SGLS365 – AUGUST 2006
www.ti.com
TA
–55°C to
125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0,17-mm Small Bump – YEA
SN74LVC2G04MYEAREP (3)
NanoFree™ – WCSP (DSBGA)
0,17-mm Small Bump – YZA
(Pb-free)
NanoStar™ – WCSP (DSBGA)
0,23-mm Large Bump – YEP
Reel of 3000
SN74LVC2G04MYZAREP (3)
SN74LVC2G04MYEPREP (3)
NanoFree™ – WCSP (DSBGA)
0,23-mm Large Bump – YZP
(Pb-free)
SOT (SOT-23) – DBV
SN74LVC2G04MYZPREP (3)
Reel of 3000 SN74LVC2G04MDBVREP(3)
SOT (SC-70) – DCK
SOT (SOT-563) – DRL
Reel of 3000
Reel of 4000
SN74LVC2G04MDCKREP
SN74LVC2G04MDRLREP (3)
TOP-SIDE MARKING(2)
BUG
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
(3) Product Preview
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
H
L
OUTPUT
Y
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
6
1Y
3
2A
4
2Y
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Features www.ti.com SN74LVC2G04-EP DUAL INVERTER GATE SGLS365 – AUGUST 2006 FEATURES • Controlled Baseline – One Assem bly Site – One Test Site – One Fabr ication Site • Extended Temperature P erformance of –55°C to 125°C • En hanced Diminishing Manufacturing Source s (DMS) Support • Ioff Supports Part ial Power-Down-Mode Operation • Latch -Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceed s JESD 22 – 2000-V Human-Body Model ( A114-A) – 200-V Machine Model (A115-A ) – 1000-V Charged-Device Model (C101 ) • Enhanced Product-Change Notifica tion • Qualification Pedigree(1) • Available in the Texas Instruments Nano Star™ and NanoFree™ Packages • Su pports 5-V VCC Operation • Inputs Acc ept Voltages to 5.5 V • Max tpd of 4. 1 ns at 3.3 V • Low Power Consumption , 10-µA Max ICC • ±24-mA Output Dri ve at 3.3 V • Typical VOLP (Output Gr ound Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C (1) Component qualification in accordan.
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