SN74LVC2G08 Gate Datasheet

SN74LVC2G08 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G08

Description

Dual 2-Input Positive-AND Gate

Manufacture

etcTI

Total Page 24 Pages
Datasheet
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SN74LVC2G08
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SN74LVC2G08
SCES198N – APRIL 1999 – REVISED DECEMBER 2015
SN74LVC2G08 Dual 2-Input Positive-AND Gate
1 Features
1 Available in the Texas Instruments
NanoStar™ and NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.7 ns at 3.3 V
• Low Power Consumption, 10-μA Maximum ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the VCC
Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• IP Phones: Wired and Wireless
• Optical Networking: EPON and Video Over Fiber
• Point-to-Point Microwave Backhaul
• Power: Telecom DC/DC Module: Analog
• Power: Telecom DC/DC Module: Digital
• Private Branch Exchange (PBX)
• Telecom Shelter: Power Distribution Unit (PDU)
• Vector Signal Analyzers and Generators
• Wireless Communications Testers
• Wireless Repeaters
• xDSL Modem/DSLAM
3 Description
This dual 2-input positive-AND gate is designed for
1.65-V to 5.5-V VCC operation.
The SN74LVC2G08 device performs the Boolean
function Y = A x B or Y = A + B in positive logic.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74LVC2G08DCT SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G08DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G08YZP DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
1A
1B 2
7
1Y
5
2A
6
2B
3
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G08
SN74LVC2G08
SCES198N – APRIL 1999 – REVISED DECEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics .......................................... 6
6.7 Typical Characteristics .............................................. 7
7 Parameter Measurement Information .................. 8
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1 Community Resources.......................................... 12
12.2 Trademarks ........................................................... 12
12.3 Electrostatic Discharge Caution ............................ 12
12.4 Glossary ................................................................ 12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (April 2014) to Revision N
Page
• Added Pin Configuration and Functions section, ESD Ratings and Thermal Information tables, Feature Description
section, Device Functional Modes section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
2 Submit Documentation Feedback
Copyright © 1999–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G08


Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC2G08 SCES198N – APR IL 1999 – REVISED DECEMBER 2015 SN74L VC2G08 Dual 2-Input Positive-AND Gate 1 Features •1 Available in the Texas Instruments NanoStar™ and NanoFree™ Package • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V Max tpd of 4.7 ns at 3.3 V • Low Po wer Consumption, 10-μA Maximum ICC • ±24-mA Output Drive at 3.3 V • Typi cal VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VC C = 3.3 V, TA = 25°C • Ioff Supports Live Insertion, Partial-Power-Down Mod e, and Back-Drive Protection • Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2 000-V Human Body Model (A114-A) – 100 0-V Charged-Device Model (C101) 2 Applications • IP Phones: Wired and Wireless • Optical Networking: EP.
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