SN74LVC2G125 Gate Datasheet

SN74LVC2G125 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G125

Description

Dual Bus Buffer Gate

Manufacture

etcTI

Total Page 27 Pages
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SN74LVC2G125
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SN74LVC2G125
SCES204Q – APRIL 1999 – REVISED MARCH 2017
SN74LVC2G125 Dual Bus Buffer Gate With 3-State Outputs
1 Features
1 ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
• Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.3 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down
to the VCC Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
2 Applications
• Cable Modem Termination Systems
• High-Speed Data Acquisition and Generation
• Military: Radars and Sonars
• Motor Controls: High-Voltage
• Power Line Communication Modems
• SSDs: Internal or External
• Video Broadcasting and Infrastructure: Scalable
Platforms
• Video Broadcasting: IP-Based Multi-Format
Transcoders
• Video Communications Systems
3 Description
The SN74LVC2G125 device is a dual bus buffer
gate, designed for 1.65-V to 5.5-V VCC operation.
This device features dual line drivers with 3-state
outputs. The outputs are disabled when the
associated output-enable (OE) input is high.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
SN74LVC2G125DCTR SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G125DCUR VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G125YZPR DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
1OE
1A 1Y
2OE
2A 2Y
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G125
SN74LVC2G125
SCES204Q – APRIL 1999 – REVISED MARCH 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions ...................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics: TA = –40°C to +85°C ...... 7
6.7 Switching Characteristics: TA = –40°C to +125°C .... 7
6.8 Operating Characteristics.......................................... 8
6.9 Typical Characteristics .............................................. 8
7 Parameter Measurement Information .................. 9
8 Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1 Documentation Support ........................................ 15
12.2 Receiving Notification of Documentation Updates 15
12.3 Community Resources.......................................... 15
12.4 Trademarks ........................................................... 15
12.5 Electrostatic Discharge Caution ............................ 15
12.6 Glossary ................................................................ 15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (January 2016) to Revision Q
Page
• Removed '200-V Machine Model' from Features for consistency with ESD ratings table. ................................................... 1
• Added orderable part numbers associated with each package. Changed US8 to VSSOP. .................................................. 1
• Updated YZP package drawing to match mechanical drawing pinout. ................................................................................. 4
• Added YZP pin identifiers to Pin Function table. Added 'buffer #' to Description for pins 2, 3, 5, and 6. Changed
'Power pin' to 'Positive supply'................................................................................................................................................ 4
• Added updated package thermal values based on new models. Changes: RθJA DCT 220 -> 199.0, DCU 227 ->
217.8, YZP 102 -> 99.8. Added: RθJCtop, RθJB, ψJT, ψJB. .......................................................................................................... 6
• Added 'Balanced Push-Pull Outputs,' 'CMOS Inputs,' 'Clamp Diodes,' 'Partial Power Down, 'Over-voltage Tolerant
Inputs.' Removed bullet list................................................................................................................................................... 10
• Added improved layout guidelines and trace example image. ............................................................................................ 13
• Added Documentation Support section, Receiving Notification of Documentation Updates section, and Community
Resources section ................................................................................................................................................................ 15
Changes from Revision O (January 2015) to Revision P
Page
• Added overbar for active low to 1OE and 2OE to the Simplified Schematic.......................................................................... 1
• Added TJ Junction temperature to the Absolute Maximum Ratings ...................................................................................... 5
• Added overbar for active low to 1OE and 2OE to the Functional Block Diagram................................................................ 10
Changes from Revision N (November 2013) to Revision O
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
2 Submit Documentation Feedback
Copyright © 1999–2017, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G125


Features Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74LVC2G125 SCES204Q – APRIL 1999 – REVISED MARCH 2017 SN74LVC2G1 25 Dual Bus Buffer Gate With 3-State Ou tputs 1 Features •1 ESD Protection E xceeds JESD 22 – 2000-V Human-Body Mo del – 1000-V Charged-Device Model • Available in the Texas Instruments Nan oFree™ Package • Supports 5-V VCC O peration • Inputs Accept Voltages to 5.5 V • Max tpd of 4.3 ns at 3.3 V Low Power Consumption, 10-µA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground Bounce) < 0 .8 V at VCC = 3.3 V, TA = 25°C • Typ ical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C • Ioff Su pports Live Insertion, Partial-Power-Do wn Mode, and Back-Drive Protection • Can Be Used as a Down Translator to Tra nslate Inputs From a Max of 5.5 V Down to the VCC Level • Latch-Up Performan ce Exceeds 100 mA Per JESD 78, Class II 2 Applications • Cable Modem Termination Systems • High-Speed Data Acquisition and Generation • Mili.
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