SN74LVC2G74-EP Flip-Flop Datasheet

SN74LVC2G74-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G74-EP

Description

Single Positive-Edge-Triggered D-Type Flip-Flop

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LVC2G74-EP Datasheet


SN74LVC2G74-EP
SN74LVC2G74-EP
www.ti.com ....................................................................................................................................................................................................... SCES718 – MAY 2008
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
FEATURES
1
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Supports 5-V VCC Operation
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Inputs Accept Voltages to 5.5 V
Max tpd of 7.9 ns at 3.3 V
Low Power Consumption, 10 µA Max ICC
±24 mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial Power Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
CLK
D
Q
GND
1
2
3
4
8 VCC
7 PRE
6 CLR
5Q
DESCRIPTION/ORDERING INFORMATION
This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial power down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated

SN74LVC2G74-EP
SN74LVC2G74-EP
SCES718 – MAY 2008 ....................................................................................................................................................................................................... www.ti.com
TA
–55°C to 125°C
VSSOP – DCU
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
Reel of 250 SN74LVC2G74MDCUTEP
CHB
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCU: The actual top-side marking has one additional character that designates the assembly/test site.
PRE
L
H
L
H
H
H
FUNCTION TABLE
CLR
H
L
L
H
H
H
INPUTS
CLK
X
X
X
L
D
X
X
X
H
L
X
OUTPUTS
QQ
HL
L
H (1)
H
H (1)
HL
LH
Q0 Q 0
PRE 7
CLK 1
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
CC
C
TG
5
Q
D2
C
TG
C
TG
C
C
TG
CLR 6
C
C
3Q
C
2 Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G74-EP


Features SN74LVC2G74-EP www.ti.com ............. ....................................... ....................................... ....................................... ....................................... .............................. SCES718 – MAY 2008 SINGLE POSITIVE EDGE TRIGG ERED D-TYPE FLIP-FLOP WITH CLEAR AND PR ESET FEATURES 1 • Controlled Baselin e – One Assembly Site – One Test Si te – One Fabrication Site • Extende d Temperature Performance of –55°C t o 125°C • Enhanced Diminishing Manuf acturing Sources (DMS) Support • Enha nced Product-Change Notification • Qu alification Pedigree (1) • Supports 5 -V VCC Operation (1) Component qualific ation in accordance with JEDEC and indu stry standards to ensure reliable opera tion over an extended temperature range . This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, aut oclave or unbiased HAST, electromigrati on, bond intermetallic life, and mold compound life. Such qualification testing should .
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