SN74LVC2G86 Gate Datasheet

SN74LVC2G86 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G86

Description

Dual 2-Input Exclusive-OR Gate

Manufacture

etcTI

Total Page 19 Pages
Datasheet
Download SN74LVC2G86 Datasheet


SN74LVC2G86
SN74LVC2G86
www.ti.com
SCES360I – AUGUST 2001 – REVISED DECEMBER 2013
Dual 2-Input Exclusive-OR Gate
Check for Samples: SN74LVC2G86
FEATURES
1
2 Available in the Texas Instruments NanoFree™
Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.7 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-
Down Mode and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This dual 2-input exclusive-OR gate is designed for
1.65-V to 5.5-V VCC operation.
The SN74LVC2G86 performs the Boolean function Y
= A B or Y = AB + AB in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
A common application is as a true/complement
element. If the input is low, the other input is
reproduced in true form at the output. If the input is
high, the signal on the other input is reproduced
inverted at the output.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
1A
1B
2Y
GND
DCT PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Y
2B
2A
DCU PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
1
2
3
4
8 VCC
7 1Y
6 2B
5 2A
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 VCC
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated

SN74LVC2G86
SN74LVC2G86
SCES360I – AUGUST 2001 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Gate)
INPUTS
AB
OUTPUT
Y
L LL
L HH
H LH
H HL
EXCLUSIVE-OR LOGIC
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74LVC2G86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT
=
EVEN-PARITY ELEMENT
2k
ODD-PARITY ELEMENT
2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
2 Submit Documentation Feedback
Copyright © 2001–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G86


Features SN74LVC2G86 www.ti.com SCES360I – AU GUST 2001 – REVISED DECEMBER 2013 Du al 2-Input Exclusive-OR Gate Check for Samples: SN74LVC2G86 FEATURES 1 •2 A vailable in the Texas Instruments NanoF ree™ Package • Supports 5-V VCC Ope ration • Inputs Accept Voltages to 5. 5 V • Max tpd of 4.7 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V • Ty pical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typica l VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Suppor ts Live Insertion, Partial-PowerDown Mo de and Back Drive Protection • Latch- Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A 114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION This dual 2-input exclusi ve-OR gate is designed for 1.65-V to 5. 5-V VCC operation. The SN74LVC2G86 perf orms the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic. NanoFree™ package technology is.
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