SN74LVC1G374 Flip-Flop Datasheet

SN74LVC1G374 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G374

Description

Single D-Type Flip-Flop

Manufacture

etcTI

Total Page 21 Pages
Datasheet
Download SN74LVC1G374 Datasheet


SN74LVC1G374
SN74LVC1G374
www.ti.com
SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013
Single D-Type Flip-Flop With 3-State Output
Check for Samples: SN74LVC1G374
FEATURES
1
2 Available in the Texas Instruments NanoStar™
and NanoFree™ Packages
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 4 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This single D-type latch is designed for 1.65-V to 5.5-
V VCC operation.
The SN74LVC1G374 features a 3-state output
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
input/output (I/O) ports, bidirectional bus drivers, and
working registers.
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
On the positive transition of the clock (CLK) input, the
Q output is set to the logic level set up at the data (D)
input.
A buffered output-enable (OE) input can be used to
place the output in either a normal logic state (high or
low logic levels) or the high-impedance state. In the
high-impedance state, the output neither loads nor
drives the bus lines significantly. The high-impedance
state and increased drive provide the capability to
drive bus lines without interface or pullup
components.
OE does not affect the internal operations of the flip-
flop. Old data can be retained or new data can be
entered while the outputs are in the high-impedance
state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DBV PACKAGE
(TOP VIEW)
CLK 1 6 OE
GND 2 5 VCC
DCK PACKAGE
(TOP VIEW)
CLK 1 6 OE
GND 2 5 VCC
D 3 4Q
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D 34 Q
GND 2 5 VCC
CLK 1 6 OE
D3
4Q
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated

SN74LVC1G374
SN74LVC1G374
SCES520C – DECEMBER 2003 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6
OE
CLK 1
3
D
Function Table
INPUTS
OE CLK
D
OUTPUT
Q
LL
L
L H
H
L H or L X
Q
HXX
Z
Logic Diagram (Positive Logic)
C1
D
4
Q
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DBV package
θJA Package thermal impedance(4)
DCK package
YEP/YZP package
–0.5
–0.5
–0.5
–0.5
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
165
259
123
V
V
V
V
mA
mA
mA
mA
°C/W
Tstg Storage temperature range
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G374


Features SN74LVC1G374 www.ti.com SCES520C – D ECEMBER 2003 – REVISED DECEMBER 2013 Single D-Type Flip-Flop With 3-State O utput Check for Samples: SN74LVC1G374 FEATURES 1 •2 Available in the Texas Instruments NanoStar™ and NanoFree™ Packages • Supports 5-V VCC Operatio n • Inputs Accept Voltages to 5.5 V Provides Down Translation to VCC • Max tpd of 4 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-m A Output Drive at 3.3 V • Ioff Suppor ts Live Insertion, Partial-PowerDown Mo de, and Back Drive Protection • Latch -Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceed s JESD 22 – 2000-V Human-Body Model ( A114-A) – 200-V Machine Model (A115-A ) – 1000-V Charged-Device Model (C101 ) DESCRIPTION This single D-type latch is designed for 1.65-V to 5.5V VCC oper ation. The SN74LVC1G374 features a 3-st ate output designed specifically for dr iving highly capacitive or relatively l ow-impedance loads. This device is particularly suitable for implementing buffer registers, input/o.
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